Available: Open Source VHDL parser - for free

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[Kelvin]

Got any Verilog parser?

Kelvin



"Sumit Gupta" <sumitg@gmail.com> wrote in message
news:82b44722.0407121536.88095e0@posting.google.com...

Hi all

I wrote a VHDL parser as part of another larger software tool about 6
years ago. The webpage, on which the parser is, is going to be
retired soon. So, if anyone is interested, here is a link to my
parser:

http://www.cecs.uci.edu/~iesag/oldPage/Topts/

Regards
Sumit

 

[Phil Tomson]

In article <40f3b85c@news.starhub.net.sg>, Kelvin <student@nowhere.com> wrote:

Got any Verilog parser?

Check out Icarus Verilog:

http://www.icarus.com/eda/verilog/

Phil

 

[Sporkman]

"danserra@id7.com" wrote:

It's handy when you have a complex design that you would like to
capture quickly and then finesse in your application of choice. A lot
depends on the skill and speed of a modeller. If you are highly
skilled and very fast, then it might not matter. This helped us on
some short timeline projects, with some difficult tasks. This device
gives you better control of your vertices than scanners.

I see no online information on a model D1. There is a model DL
(actually 3DL), but not a D1.

 

[Eyck Jentzsch]

It's TCL so $env(...) does the job.

-Eyck

 

[ka]

On 22 Aug 2004 14:25:25 -0700, yxl4444@louisiana.edu (Lee) wrote:

Someone told me that synthesis tool can calculate the gate count
automatically. But I don't know how. For example, in Synopsys Design
Compiler, calculate the gate (NAND) count for a design.

Thanks

Adrian

You can do this by generating an area report (report_area -hier ).
This shows you the area of all blocks in some unit. This unit depends
on the cell library you used. To get the NAND2 count for the design,
you need to find out the size of the 1x drive NAND2 cell and divide
the total size to that number.

 

[ka]

On 23 Aug 2004 07:14:52 -0700, yxl4444@louisiana.edu (Lee) wrote:

Hi,

What is the gate in "the gate count" mentioned by papers?NAND or NOR
or Inverter?

If I use the different basic gate, the gate count for a design could
be different. What is the usual way?

The gate count is usually NAND2 with a 1x drive.

 

[Larry Horse]

ass