Automatic VHDL Generating

[Vhdl.eu]

Hi all,

I am investigating programs that do automatic VHDL generating. Like there
are Matlab/Simulink and LabVIEW.

I have heard that there are some other tools/programs online (for free)
where you can generate for instance filters from a VB.NET program. Has
anyone got some links for this which he can share so I can see how those
persons are implementing this?

thanks in advance and Kind regards,
http://www.vhdl.eu

 

[Jeremy Ralph]

The company I represent, PDTi (http://www.productive-eda.com) provides
SpectaReg, a tool that generates code and docs for memory mapped
registers (MMR). It captures MMR specs then can generate:

* RTL implementation (verilog, vhdl)
* self checking verification platform (SystemVerilog, VHDL, e, ...)
* C/C++ to abstract registers/bitfields
* datasheet (HTML, DocBook, DITA, Framemaker, ...)
* System level C/C++ memory-map tests

This enables significant efficiency improvements, reducing errors and
allowing engineers to focus on value added development. Perhaps the
most value comes from SpectaReg's ability to synchronize the various
code and doc views with the golden spec. Certainly debugging a
datasheet or software driver that doesn't match the RTL can be
frustrating and time consuming-- SpectaReg eliminates this.

Best Regards,
Jeremy


---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps


Vhdl.eu wrote:

Hi all,

I am investigating programs that do automatic VHDL generating. Like there
are Matlab/Simulink and LabVIEW.

I have heard that there are some other tools/programs online (for free)
where you can generate for instance filters from a VB.NET program. Has
anyone got some links for this which he can share so I can see how those
persons are implementing this?

thanks in advance and Kind regards,
http://www.vhdl.eu

 

[Ralf Hildebrandt]

Vhdl.eu wrote:

I am investigating programs that do automatic VHDL generating. Like there
are Matlab/Simulink and LabVIEW.

The generation of VHDL code is not a real problem - the problem is the
purpose of the generator (in other words the problem you have to solve).
As you have mentioned digital filters are generated by some tools
(because their structure can be parameterised). Another purpose might be
the generation of state machines.

If you have a very special problem where no tool exists, that maps this
problem to VHDL you can "easily" write your own generator. You are
completely free, how to realize this generator. E.g. I have done a
generator, that modifies VHDL VITAL libraries for a special purpose.
This "generator" is nothing more than an ASCII text parser and ASCII
text generator. I have chosen ANSI C as base for my generator - just
because that's a language I know. ;-)

Ralf