Automatic verilog module composer/decomposer?

[Jim]

Hello,

I have a bunch of verilog design files, and what I need to do is to
flatten the design hierarchy and compose new modules according to the
specification. I don't want to do it manually, and would like to know
if any free/commercial tool can do it automatically. I know Design
Compiler can do this, but it can only generate verilog files that are
quite difficult to read, since some nets are missing and some buses
disappear during ungroup/group in the generated files. I appreciate if
anyone can tell me an easy way to do it.

Thanks,
Feng

 

[Michael]

You can use ncverilog with "-d" option.
ncverilog -d file1.v file2.v

 

[Jim]

Thanks for your reply. If I remember correctly "-d" means "-define".
Can you give me more instructions on how to do it?

-Jim

Michael wrote:

You can use ncverilog with "-d" option.
ncverilog -d file1.v file2.v

 

[Rob Dekker]

Hi Jim,

The 'design' files, are they RTL files ?
Or do you want to do the flattening/grouping after synthesis (on a gate level netlist) ?

I do not know of any RTL level Verilog flattener. Actually I would be surprised if there
would be any, since Verilog does not have any appropriate constructs to flatten the
instantiations into (no 'block').

But if you need to do this work at gate-level, then any synthesis tool should be able to help you out.
But flattening DOES merge nets from different hierarchy levels. Not much way around that...

Rob

"Jim" <feng.shi@gmail.com> wrote in message news:1162186715.942446.326870@k70g2000cwa.googlegroups.com...

Hello,

I have a bunch of verilog design files, and what I need to do is to
flatten the design hierarchy and compose new modules according to the
specification. I don't want to do it manually, and would like to know
if any free/commercial tool can do it automatically. I know Design
Compiler can do this, but it can only generate verilog files that are
quite difficult to read, since some nets are missing and some buses
disappear during ungroup/group in the generated files. I appreciate if
anyone can tell me an easy way to do it.

Thanks,
Feng

 

[Michael]

You remember incorrectly. To make a macro definition you have to use
"+define+macro".
Check your help screen of ncverilog/verilog command.

Usage:
ncverilog [all valid Verilog-XL arguments]

Supported Dash options:
-c Parse(compile) and elaborate, do NOT
simulate
-d Decompile
-f <filename> Read host command arguments from file
-h Print this help message
-k <filename> Set key file name
-l <filename> Set log file name
-Q Quiet mode with tool banner and command
line options
-q Suppress Informational messages(i.e.
Quiet mode)
-R Simulate using last snapshot generated
-r <snapshot name> Force Simulation using snapshot. Do not
compile or elaborate
-s Enter interactive mode immediately
-u Convert identifiers to upper case
-v <filename> Specify a library file to be used
-y <directory> Specify a library directory to be used

Jim wrote:

Thanks for your reply. If I remember correctly "-d" means "-define".
Can you give me more instructions on how to do it?

-Jim

Michael wrote:
You can use ncverilog with "-d" option.
ncverilog -d file1.v file2.v