automatic placement/routing within a cell

Hi,
is there any way in cadence virtuoso to do the following:
Say a transistor has "n" fingers.Is it possible to short all the
source and drain connections and poly connections of that transistor
(other than manual routing)??
Or
should we write code in skill to do this...
If so can you give some inputs on this....

 

Will the "Virtuoso Custom Placement and Routing " help in this
regard??
If so could you please suggest me how to proceed....



On May 12, 11:40 am, lokeshr...@gmail.com wrote:

Hi,
is there any way in cadence virtuoso to do the following:
Say a transistor has "n" fingers.Is it possible to short all the
source and drain connections and poly connections of that transistor
(other than manual routing)??
Or
should we write code in skill to do this...
If so can you give some inputs on this....

 

[Tarek]

Depends on how robust your pcells are. I've worked with kits from IBM
and TSMC, and the IBM pcells are excellent (support shorting S and D
for multifinger transistors, merging of parallel and series
transistors). For TSMC we could not define fingers at the schematic
level, it had to be defined at the layout level which causes LVS
problems. In my experience, VCAR isn't that smart of a router. You
need to be very meticulous when defining the rules and still it will
make bad routes. After several 'cleanup's it can produce a half-decent
job.

 

[Riad KACED]

Hi Guys,

Yes, best way is to enhance your Pcell. Otherwise, if you have an
equivalent symbol in the schematic, then you should be able to quickly
run this routing. Again if your Pcell is well written. Tarek, I don't
know which TSMC PDK you are using but TSMC does provide pretty good
Pcells nowadays, with fingers and auto-routing of the S/D diffusion,
poly gates ... etc. I find the TSMC Pcells pretty good actually. You
might need to get in touch with your TSMC account manager or move
forward with a new PDK.

Cheers,
Riad.

 

Thanks riad,
I guess then i have to read upon have to create pcells using skill..
hence I'm currently referring to the following manual(Virtuoso
Parameterized Cell Reference)...
hope I'm in the right direction..

hey Riad and you didnt comment on "Virtuoso Custom Placement and
Routing " .....
Eagerly waiting for comments from people..

Regards,
Lokesh rajendran...




On May 13, 4:37 am, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Guys,

Yes, best way is to enhance your Pcell. Otherwise, if you have an
equivalent symbol in the schematic, then you should be able to quickly
run this routing. Again if your Pcell is well written. Tarek, I don't
know which TSMC PDK you are using but TSMC does provide pretty good
Pcells nowadays, with fingers and auto-routing of the S/D diffusion,
poly gates ... etc. I find the TSMC Pcells pretty good actually. You
might need to get in touch with your TSMC account manager or move
forward with a new PDK.

Cheers,
Riad.

 

[Riad KACED]

Hi Lokesh,

Yes you are on the right direction towards the Pcell doc.
I didn't comment on the VCAR bit because I don't have the relevant
experience to share any useful and fair comments about it. My
knowledge of the Cadence tools is lacking many bricks I'm afraid :-(

Sorry for that :$

Cheers,
Riad.

 

[Andrew Beckett]

Riad KACED wrote, on 05/13/09 13:14:

Hi Lokesh,

Yes you are on the right direction towards the Pcell doc.
I didn't comment on the VCAR bit because I don't have the relevant
experience to share any useful and fair comments about it. My
knowledge of the Cadence tools is lacking many bricks I'm afraid :-(

Sorry for that :$

Cheers,
Riad.

There's also a lot of capability in IC613 for this - for example, modgens, an
analog placer, and so on. In IC5141 you could use NeoCell, but the setup is
relatively complex compared with IC613 where the NeoCell technology is
integrated into the environment.

This still in IC613 is in Virtuoso Layout Suite GXL - here's the datasheet -
http://www.cadence.com/rl/Resources/datasheets/virtuoso_platform_GXL.pdf

Regards,

Andrew.