T
Thomas Thorsen
Guest
I have been trying to create a 20bit adder/subtractor in VHDL, but no matter
how i define it, Quartus II won't infer the appropriate megafunction
lpm_add_sub. Even if i use the code that can be downloaded from:
http://www.altera.com/support/examples/vhdl/vhd-add-sub.html
it still does not infer the lpm_add_sub as it should, according to the
description. The reason i want this, is that my adder takes up 41 logic
cells. If i directly instantiate the lpm_add_sub it only takes up 21 logic
cells (the 2's complement negation is merged into the same logic cells).
However, if i directly instantiate the lpm_add_sub the code is not general
VHDL anymore and i need that to (for simulation in ModelSim that does not
know about the megafunctions). So question is, how do i tell Quartus II that
my adder should be implemented as an lpm_add_sub (automatic inference)?
Any helpfull comments are greatly appreciated.
how i define it, Quartus II won't infer the appropriate megafunction
lpm_add_sub. Even if i use the code that can be downloaded from:
http://www.altera.com/support/examples/vhdl/vhd-add-sub.html
it still does not infer the lpm_add_sub as it should, according to the
description. The reason i want this, is that my adder takes up 41 logic
cells. If i directly instantiate the lpm_add_sub it only takes up 21 logic
cells (the 2's complement negation is merged into the same logic cells).
However, if i directly instantiate the lpm_add_sub the code is not general
VHDL anymore and i need that to (for simulation in ModelSim that does not
know about the megafunctions). So question is, how do i tell Quartus II that
my adder should be implemented as an lpm_add_sub (automatic inference)?
Any helpfull comments are greatly appreciated.