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Hey I have a library of digital cells in Layout view .
I need to create a schematic view for this cells automaticly.
Is there any way to do it?
Dmitriy
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
Kev, is this a dump of the template from cdlin? It doesn't look like
it. Can you include that? It looks like you have some fields missing in
this post. Is KK_work library tied to the PDK techfile or does it have
it's own?
David
On Jan 26, 7:18 am, "kev" <kevin.kelli...@gmail.com> wrote:
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
Here is the dump.....all libs tied to the pdk techfile...
cdlInKeys = list(nil
'searchPath "./cdl"
'cdlFile "netlist"
'userSkillFile ""
'devMapFile ""
'opusLib "AA_CDL"
'primaryCell "test18vinv"
'caseSensitivity "preserve"
'hierarchy "full"
'cellTable ""
'viewName "schematic"
'viewType "schematic"
'pr nil
'skipDevice nil
'schGenOption t
'schGenParamFile "/tmp/c2s.opt1099951567"
'refLibList "tsmc18rf "
'globalNodeExpand "full"
'overwriteExistingCVs "all"
)
On Jan 26, 2:09 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, is this a dump of the template from cdlin? It doesn't look like
it. Can you include that? It looks like you have some fields missing in
this post. Is KK_work library tied to the PDK techfile or does it have
it's own?
David
On Jan 26, 7:18 am, "kev" <kevin.kelli...@gmail.com> wrote:
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
Kev, what version of cadence are you using? Based on this dump, it
looks like you are using an old version, is this true? I was expecting
to see a schemaLib filed (or something like that)
If that is true, your best bet may be to write some skill to map the
primitives into your pdk devices. As I recall, the ability to specify
pdk primitive devices came in ~ 5.141 (I am sure someone will correct
me if I am wrong)
David
On Jan 26, 9:19 am, "kev" <kevin.kelli...@gmail.com> wrote:
Here is the dump.....all libs tied to the pdk techfile...
cdlInKeys = list(nil
'searchPath "./cdl"
'cdlFile "netlist"
'userSkillFile ""
'devMapFile ""
'opusLib "AA_CDL"
'primaryCell "test18vinv"
'caseSensitivity "preserve"
'hierarchy "full"
'cellTable ""
'viewName "schematic"
'viewType "schematic"
'pr nil
'skipDevice nil
'schGenOption t
'schGenParamFile "/tmp/c2s.opt1099951567"
'refLibList "tsmc18rf "
'globalNodeExpand "full"
'overwriteExistingCVs "all"
)
On Jan 26, 2:09 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, is this a dump of the template from cdlin? It doesn't look like
it. Can you include that? It looks like you have some fields missing in
this post. Is KK_work library tied to the PDK techfile or does it have
it's own?
David
On Jan 26, 7:18 am, "kev" <kevin.kelli...@gmail.com> wrote:
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
It's a linux version , 5.10.41.500.....
also, i have found out that if i run the cdlinin the following way i
get
some kind of schematic .
run cdlin once with P&R option selected -> generates mos->abstract
cellview
rerun cdlin a second time unchagned -> topcell-> maskLayoutview
rerun a 3rd time with P&R deselected -> topcel-> schematic view.
however, it imports use the rather crude local "mos" cell view both for
pmos and nmos device.....
so i need to write a map file to map P/N to my pmos/nmso in device
lib??
Kevin
On Jan 26, 2:46 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, what version of cadence are you using? Based on this dump, it
looks like you are using an old version, is this true? I was expecting
to see a schemaLib filed (or something like that)
If that is true, your best bet may be to write some skill to map the
primitives into your pdk devices. As I recall, the ability to specify
pdk primitive devices came in ~ 5.141 (I am sure someone will correct
me if I am wrong)
David
On Jan 26, 9:19 am, "kev" <kevin.kelli...@gmail.com> wrote:
Here is the dump.....all libs tied to the pdk techfile...
cdlInKeys = list(nil
'searchPath "./cdl"
'cdlFile "netlist"
'userSkillFile ""
'devMapFile ""
'opusLib "AA_CDL"
'primaryCell "test18vinv"
'caseSensitivity "preserve"
'hierarchy "full"
'cellTable ""
'viewName "schematic"
'viewType "schematic"
'pr nil
'skipDevice nil
'schGenOption t
'schGenParamFile "/tmp/c2s.opt1099951567"
'refLibList "tsmc18rf "
'globalNodeExpand "full"
'overwriteExistingCVs "all"
)
On Jan 26, 2:09 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, is this a dump of the template from cdlin? It doesn't look like
it. Can you include that? It looks like you have some fields missing in
this post. Is KK_work library tied to the PDK techfile or does it have
it's own?
David
On Jan 26, 7:18 am, "kev" <kevin.kelli...@gmail.com> wrote:
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG
David,
OK got the device map to work, only problem left is that the total
width doesn't
update on the nmos/pmos symbol.
w=2u for all devices, which i guess is the default in my cdf.
any ideas how to fix this (gonna look thru' doc/newsgroup now)
Kevin
On Jan 26, 2:59 pm, "kev" <kevin.kelli...@gmail.com> wrote:
It's a linux version , 5.10.41.500.....
also, i have found out that if i run the cdlinin the following way i
get
some kind of schematic .
run cdlin once with P&R option selected -> generates mos->abstract
cellview
rerun cdlin a second time unchagned -> topcell-> maskLayoutview
rerun a 3rd time with P&R deselected -> topcel-> schematic view.
however, it imports use the rather crude local "mos" cell view both for
pmos and nmos device.....
so i need to write a map file to map P/N to my pmos/nmso in device
lib??
Kevin
On Jan 26, 2:46 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, what version of cadence are you using? Based on this dump, it
looks like you are using an old version, is this true? I was expecting
to see a schemaLib filed (or something like that)
If that is true, your best bet may be to write some skill to map the
primitives into your pdk devices. As I recall, the ability to specify
pdk primitive devices came in ~ 5.141 (I am sure someone will correct
me if I am wrong)
David
On Jan 26, 9:19 am, "kev" <kevin.kelli...@gmail.com> wrote:
Here is the dump.....all libs tied to the pdk techfile...
cdlInKeys = list(nil
'searchPath "./cdl"
'cdlFile "netlist"
'userSkillFile ""
'devMapFile ""
'opusLib "AA_CDL"
'primaryCell "test18vinv"
'caseSensitivity "preserve"
'hierarchy "full"
'cellTable ""
'viewName "schematic"
'viewType "schematic"
'pr nil
'skipDevice nil
'schGenOption t
'schGenParamFile "/tmp/c2s.opt1099951567"
'refLibList "tsmc18rf "
'globalNodeExpand "full"
'overwriteExistingCVs "all"
)
On Jan 26, 2:09 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, is this a dump of the template from cdlin? It doesn't look like
it. Can you include that? It looks like you have some fields missing in
this post. Is KK_work library tied to the PDK techfile or does it have
it's own?
David
On Jan 26, 7:18 am, "kev" <kevin.kelli...@gmail.com> wrote:
Hi David,
OK here is what I did,
I took a nmos and pmos transistor, simply placed them and did a cdl
out.
then I try to import with cdlin witht the followoing fields set:
"searchpath" = .
"cdl file = /home/..../cdl/netlist (output netlist from cdl out..)
"userskill file" blank
"device mapping file" blank
"topecellname" = test18inv (same as what is in netlist)
"case sensitivity" = preserve
"hierarcchy" = full
"top lvelcell table" blank
"target library" = myLib (existing)
"view name" = schematic
"view type" = schematic
" reference lib list" = tsmc18rf analogLib basic
"use for P&R" not selected
"skip primitive library" not selected
"global node expand" full
"create schematic" selected
"schematic generation options" are defaults and has extract schematics
extracted..
the cdl netlist looks like:
************************************************************************
* auCdl Netlist:
*
* Library Name: KK_WORK
* Top Cell Name: test18vinv
* View Name: schematic
* Netlisted on: Jan 26 12:05:16 2007
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
************************************************************************
* Library Name: KK_WORK
* Cell Name: test18vinv
* View Name: schematic
************************************************************************
.SUBCKT test18vinv
*.PININFO
MM1 net1 net3 net4 net2 P l=180n w=2u m=1
MM0 net5 net7 net8 net6 N l=180n w=2u m=1
.ENDS
[ I have tried without all the comments as well just in case?! But I
guess cdlin should
be able to read the result of a cdl out?!? ]
The result is a cell named mos which has the pins S,D,G,B in a
schematic.
So the problem is somehow in the mapping of the primitives, If I ignore
schematics
I at least get a top level black box schemaitc for test18in cell with
nothing inside which is what I expect since
I don't ahve any pins (If I add pins then these appear..)
any ideas?
regards
Kev
On Jan 16, 8:39 pm, "DReynolds" <spurwinkt...@gmail.com> wrote:
Kev, it sounds like you are not pointing to the PDK when you run cdlin,
so it does not know where to find the primitives....
can you tell me what you have int the fields of the template?
David
kev wrote:
it's created in my import library.
The cdlin script imports the schematic and i have only 1 cell view =
mos
which has only a symbol view [which seems to be actually a schematic
as it contains 4 mos terminals/pins [d,g,s,b] that are in a schematic]
from what i have read this cdlin seems to be straight forward thus my
conclusion is that
it is a problem with the linux version of cadence and not a user
problem!
DReynolds wrote:
Kev, when you say just a MOS symbol, what is exact name and what is the
library it comes from?nfet,pfet,from library sample?
Does your process have multiple types of fets primitives? low vt,
normal, high voltage,etc?
David
kev wrote:
Hi
The problem is I don't get anything. Just a mos symbol if I say not to
skip primitives.
If I skip primitives then I jsut get pins in the schematic which is
what I would expect.
I set the ref lib to device lib where the primitives are.
Kevin
DReynolds wrote:
If you have a netlist file for your cell it is probably in spice or CDL
format which means you can run cdlin on it.
in CIW window ->import->cdlin
it will ask you some basic stuff about what library do you want to put
the cell in,etc. After it makes the schematic, open it up and make sure
it looks ok... no dangling wires, no symbols that are huge or non
existent, etc. Once you have a clean schematic, you can try to export
it.
If it looks ok, then check and see what the devices are called, are
they coming from your PDK or are they default devices from sample...
this is a common issue for first time importing.
David
kev wrote:
Hi
I have tried this cdlin but can't get it to work.
I have even exported a schematic and read it back in. The best I can
manage is to
get the pins but no devices.
I am running on linux, cadence 5.10.xxxx
Kevin
Dmitriy Shurin wrote:
Thanks but I didn't find the exact command in CIW can you explain me in
details how to do it
And cdl files are supposed to be a file in each cell (some kind of a
netlist)?
Thanks
--
Posted via Mailgate.ORG Server -http://www.Mailgate.ORG