Automated testing a la junit?

[Jan Decaluwe]

Guenter Dannoritzer wrote:

Jules wrote:

Perhaps this is an odd request, but does anyone know of anything like
junit for verilog? For those unfamiliar, what I'm looking for is a
framework that makes it simple to set up testbenches, including
specifying how to interact with the system under test and what the
results should be, and a user interface that runs through a list of
these testbenches, showing an easily-read summary of which tests
passed and which failed.



I am using the unittest package from Python in connection with MyHDL.

http://docs.python.org/lib/module-unittest.html

MyHDL allows to do Co-Simulation with Verilog and the unittest package
is based on the junit idea. So you can create several test cases and run
them. Unittest will give you a nice output in text form or even with
GUI. It contains various assert statements which allow you to do
assertion based verification.

I'd like to add that there other unit test frameworks that one
can use in Python. 'py.test' deservers to be mentioned, because
it is extremely non-intrusive and therefore feels more "pythonic".
A disadvantage is that it is not part of Python's standard library.

For a MyHDL example with 'py.test', see here:

http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com

 

[Jules]

Perhaps this is an odd request, but does anyone know of anything like
junit for verilog? For those unfamiliar, what I'm looking for is a
framework that makes it simple to set up testbenches, including
specifying how to interact with the system under test and what the
results should be, and a user interface that runs through a list of
these testbenches, showing an easily-read summary of which tests
passed and which failed.

 

[Mike Treseler]

Jules wrote:

Perhaps this is an odd request, but does anyone know of anything like
junit for verilog? For those unfamiliar, what I'm looking for is a
framework that makes it simple to set up testbenches, including
specifying how to interact with the system under test and what the
results should be, and a user interface that runs through a list of
these testbenches, showing an easily-read summary of which tests
passed and which failed.

The execution environment for a hardware description
language is a simulator. Scripting of multiple
simulation runs may be done in tcl or shell.
I use editor templates for testbench boilerplate
but only the designer can know what an
appropriate stimulation and verification process
should be.

-- Mike Treseler

 

[Guenter Dannoritzer]

Jules wrote:

Perhaps this is an odd request, but does anyone know of anything like
junit for verilog? For those unfamiliar, what I'm looking for is a
framework that makes it simple to set up testbenches, including
specifying how to interact with the system under test and what the
results should be, and a user interface that runs through a list of
these testbenches, showing an easily-read summary of which tests
passed and which failed.

I am using the unittest package from Python in connection with MyHDL.

http://docs.python.org/lib/module-unittest.html

MyHDL allows to do Co-Simulation with Verilog and the unittest package
is based on the junit idea. So you can create several test cases and run
them. Unittest will give you a nice output in text form or even with
GUI. It contains various assert statements which allow you to do
assertion based verification.

For some examples see the MyHDL manual:

http://www.jandecaluwe.com/Tools/MyHDL/manual/unittest-intro.html


Cheers,

Guenter