Auto-generating schematics using SKILL

[NigelD]

Hi,

I'm a grad student and have used Cadence before, but I'm pretty new to
using SKILL. I'd appreciate any help I can get with the following
problem:

I'm trying to auto-generate schematics in Virtuoso and I can not figure
out how to actually draw a wire. I've used dbCreateNet and
dbCreateConnByName to create a net and connect terminals to that net.
However, I would also like to somehow draw the wire connection using
SKILL. Normally you would do Add->Wire and click on the terminals you
wanted to connect if using the graphical editor. Is there a SKILL
function that will do the equivalent?

Thanks,
Nigel.

 

[John Gianni]

NigelD wrote:

I'm trying to auto-generate schematics in Virtuoso ...

Others can answer the specific question you posed; I'll take the more
general approach by referring listeners to the existing schematic
generation capability within the later versions of the Cadence Virtuoso
schematic editor. That is, IIRC, given a Spice, Spectre, CDL, or
Verilog HDL text netlist, the Cadence schematic generator will generate
the complete schematic, including wire routing between instances. Of
course, EDIF would do it also.

Hope this gives you another avenue to resolve the need to generate
schematics.
As I said, others can answer for the specific SKILL functions
requested.

John Gianni
-- Nothing stated by me on the USENET is prior reviewed by my employer!

 

[Andrew Beckett]

On 22 Feb 2006 12:24:44 -0800, "NigelD" <ndrego@gmail.com> wrote:

Hi,

I'm a grad student and have used Cadence before, but I'm pretty new to
using SKILL. I'd appreciate any help I can get with the following
problem:

I'm trying to auto-generate schematics in Virtuoso and I can not figure
out how to actually draw a wire. I've used dbCreateNet and
dbCreateConnByName to create a net and connect terminals to that net.
However, I would also like to somehow draw the wire connection using
SKILL. Normally you would do Add->Wire and click on the terminals you
wanted to connect if using the graphical editor. Is there a SKILL
function that will do the equivalent?

Thanks,
Nigel.

schCreateWire()

You'll find the sch.* functions an easier way of doing this than having to
create all the nets and shapes yourself.

Search in cdsdoc - there's a whole manual on the Composer SKILL functions. For
the cdsdoc-challenged, it's in <instdir>/doc/skcompref/skcompref.pdf

Regards,

Andrew.

 

[NigelD]

Thanks for tip on the schematic generator. I'm using CDL In but how do
you specify lengths and widths for transistors? The transistors I'm
using are from a design kit and are in their own library, so in the CDL
netlist I specified them as subcircuits (i.e. XPMPASS vdd g vddv<0> vdd
pmos2v l=0.36e-6 w=2e-6) and put the reference library as the library
in which pmos2v is located. If I had made it MPMPASS then CDL in tries
to create a mos4 symbol and has problems doing it, so I have to make it
a subcircuit to get it to generate the schematic. But it doesn't do
anything with W and L. pmos2v is a parameterized cell, is there any way
of specifying the parameters in the CDL netlist?

Thanks,
Nigel.

 

[Bernd Fischer]

There is a SourceLink solution for this:
http://sourcelink.cadence.com/docs/db/kdb/2004/Nov/11160008.html
but take care, have also a look at this one:
http://sourcelink.cadence.com/docs/db/kdb/2005/Sept/11193692.html
Maybe that helps.

Bernd

NigelD wrote:

Thanks for tip on the schematic generator. I'm using CDL In but how do
you specify lengths and widths for transistors? The transistors I'm
using are from a design kit and are in their own library, so in the CDL
netlist I specified them as subcircuits (i.e. XPMPASS vdd g vddv<0> vdd
pmos2v l=0.36e-6 w=2e-6) and put the reference library as the library
in which pmos2v is located. If I had made it MPMPASS then CDL in tries
to create a mos4 symbol and has problems doing it, so I have to make it
a subcircuit to get it to generate the schematic. But it doesn't do
anything with W and L. pmos2v is a parameterized cell, is there any way
of specifying the parameters in the CDL netlist?

Thanks,
Nigel.

 

[NigelD]

Being a grad student, I unfortunately do not have access to SourceLink,
and I don't think the admins here will give me the necessary info to
get a SourceLink account . Is there anyway you might be able to post
those pages here?

Thanks,
Nigel.

 

[DReynolds]

Nigel, one way that I have used in the past is to leave the transistors
in the cdl as primitives, run cdlIn and then do a swap for the pfet to
pmos2v. This has the advantage of bringing in all the w,l info but it
can get a bit tricky if you have lots of different kinds of transistors
in your schematic.

David

 

[John Gianni]

John Gianni wrote:

NigelD wrote:
I'm trying to auto-generate schematics in Virtuoso ...

Others can answer the specific question you posed; I'll take the more
general approach by referring listeners to the existing schematic
generation capability within the later versions of the Cadence Virtuoso
schematic editor. That is, IIRC, given a Spice, Spectre, CDL, or
Verilog HDL text netlist, the Cadence schematic generator will generate
the complete schematic, including wire routing between instances.

The question came up as to WHICH versions of DFII Virtuoso schematic
editor support Spice, Spectre & CDL human-readable schematic
generation.capabilities.

Schematic generation from EDIF, CDL, & Verilog capability exists today
- while the schematic generation from Spice & Spectre netlists or a mix
thereof is the subject of Cadence enhancement product change request
#657762 which has been added to the latestVirtuoso IC61 release
currently under beta testing.

John Gianni
-- Nothing posted by me here is prior reviewed nor sanctioned by my
employer