Auto completion for Verilog and System Verilog

[Orly]

Hi,

I am want to write an auto completion feature for a Verilog and SV IDE
which includes the following features:
1. Word completion.
2. Member completion.
3. Parameter completion

I am looking for all the material I can find that can help me get ideas
on how to implement such feature.

Do you have any suggestions/links you can point me up for open
sources/articles on this subject?

Thanks,
Orly

 

[Ajeetha]

Hi,
I created an emacs mode file for SV that would do these stuff quite
well. Biggest problem I've is the indentation. Honestly I'm not a LISP
expert, rather hacked some old VERA/JEDA/PSL mode to work for SV. I can
send it to you (or upload to noveldv.com, but that would take few days)
if send me an email to gmail.com @ ajeetha

Disclaimer: It is a not a well written mode file, atleast one user
didn't like it so much so no high expectations please. I like it simply
for the "word completion" and nothing else. I've not spent enough time
in updating/maintaining it as I'm busy with other stuff.

BTW - which IDE are you targetting?

Regards
Ajeetha
www.noveldv.com