H
Hubble
Guest
Inside testbenches, it is often the case that multiple instances of
some stimuli (think ethernet interfaces, PCI busses) have a generic
number (G_ETHERNET_INTERFACE_NO) which is then set to 0, 1, 2, ...
manually.
I want to auto-initialize such interfaces, which means that each such
interface has a shared variable or signal (interface_no) and an init
process, say like this:
architecture tst of einterface is
shared variable interface_no: natural;
begin
...
Get_Interface_No: process
begin
alloc_number(interface_no);
wait;
end;
end;
A package should provide the alloc_number procedure:
package allocator is
procedure alloc_number(variable n: out natural);
end allocator;
package body allocator is
shared variable numbers: natural:=0;
procedure alloc_number(variable n: out natural) is
begin
n:=numbers;
numbers:=number+1;
end;
end allocator;
If you use 10 interfaces, the interfaces should get different interface
numbers from 0 to 9. The order is insignificant, but is is required
that all interfaces get their own number.
While this works on my Modelsim 6 on my single processor machine, it is
not portable in VHDL'93. The LRM states, that if shared variables are
accessed in the same simulation cycle (like here), we can assume
*nothing* about the order of execution (not a problem here) and also if
(the problem here) the accesses are sequential:
"A description is erroneous if it depends on whether or how an
implementation sequentializes access to shared variables."
Is there a way in VHDL'93 do solve this problem (in a portable, non
erroneous way)?
Hubble
some stimuli (think ethernet interfaces, PCI busses) have a generic
number (G_ETHERNET_INTERFACE_NO) which is then set to 0, 1, 2, ...
manually.
I want to auto-initialize such interfaces, which means that each such
interface has a shared variable or signal (interface_no) and an init
process, say like this:
architecture tst of einterface is
shared variable interface_no: natural;
begin
...
Get_Interface_No: process
begin
alloc_number(interface_no);
wait;
end;
end;
A package should provide the alloc_number procedure:
package allocator is
procedure alloc_number(variable n: out natural);
end allocator;
package body allocator is
shared variable numbers: natural:=0;
procedure alloc_number(variable n: out natural) is
begin
n:=numbers;
numbers:=number+1;
end;
end allocator;
If you use 10 interfaces, the interfaces should get different interface
numbers from 0 to 9. The order is insignificant, but is is required
that all interfaces get their own number.
While this works on my Modelsim 6 on my single processor machine, it is
not portable in VHDL'93. The LRM states, that if shared variables are
accessed in the same simulation cycle (like here), we can assume
*nothing* about the order of execution (not a problem here) and also if
(the problem here) the accesses are sequential:
"A description is erroneous if it depends on whether or how an
implementation sequentializes access to shared variables."
Is there a way in VHDL'93 do solve this problem (in a portable, non
erroneous way)?
Hubble