K
Kunal
Guest
Hi,
I want to auto increment 8 bit addresses whenever there is a start
pulse involved and stop increment for stop pulse. assign input data to
that incremented memory location. (data is 8 bits as well...)
Verilog....
Any help will appreciated.
// will this do?
wire_address = 0;
always@(posedge CLK)
assign data = wire_data;
assign address = wire_address;
if(start & !stop)
begin
for (wire_address = 0; wire_address <= memory_max ; wire_address =
wire_address + 1);
begin
memory[wire_address] = data [7:0]
end
end
else if (!start & stop)
// please advice description here
else if (start & stop )
//description here
or there is another and efficient way?
Thanks in advance.
KV
I want to auto increment 8 bit addresses whenever there is a start
pulse involved and stop increment for stop pulse. assign input data to
that incremented memory location. (data is 8 bits as well...)
Verilog....
Any help will appreciated.
// will this do?
wire_address = 0;
always@(posedge CLK)
assign data = wire_data;
assign address = wire_address;
if(start & !stop)
begin
for (wire_address = 0; wire_address <= memory_max ; wire_address =
wire_address + 1);
begin
memory[wire_address] = data [7:0]
end
end
else if (!start & stop)
// please advice description here
else if (start & stop )
//description here
or there is another and efficient way?
Thanks in advance.
KV