Audio output from a Nexys 4 board

[Maj55]

I am learning verilog using a Nexys 4 board. I have written the code below for audio output from the board. I am sending a square wave to the audio port, but there is no audio output. What am I doing wrong here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

 

[GaborSzakacs]

Maj55 wrote:

I am learning verilog using a Nexys 4 board. I have written the code below for audio output from the board. I am sending a square wave to the audio port, but there is no audio output. What am I doing wrong here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

Without seeing the board schematics, my first guess is that
the "ampPWM" output goes through some filtering to create
audio. So giving it a constant 50% square wave would actually
just output a 50% level (DC) on the audio.

On the other hand it's also quite likely that you didn't
assign the pins correctly and you are either not actually
getting a clock, or not actually driving the correct pin to
output audio.

By the way, you've defined "counter" as an output port. If
you don't want the counter to be output on a random set of
16 pins, you should move that into the body of the module.

--
Gabor

 

[rickman]

On 10/29/2014 1:12 PM, Maj55 wrote:

I am learning verilog using a Nexys 4 board. I have written the code below for audio output from the board. I am sending a square wave to the audio port, but there is no audio output. What am I doing wrong here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

There is no point in downloading to a chip before you have simulated the
code. Have you run a simulation?

--

Rick

 

[GaborSzakacs]

rickman wrote:

On 10/29/2014 1:12 PM, Maj55 wrote:
I am learning verilog using a Nexys 4 board. I have written the code
below for audio output from the board. I am sending a square wave to
the audio port, but there is no audio output. What am I doing wrong here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

There is no point in downloading to a chip before you have simulated the
code. Have you run a simulation?

Rick,

If your entire code consists of a 16-bit up counter with
reset, do you really need to simulate it? My guess is that
the code does exactly what he expects. It's something outside
the coding / simulation environment (i.e. board level pin
assignment and circuitry) that is screwing up.

--
Gabor

 

[rickman]

On 10/30/2014 3:55 PM, GaborSzakacs wrote:

rickman wrote:
On 10/29/2014 1:12 PM, Maj55 wrote:
I am learning verilog using a Nexys 4 board. I have written the code
below for audio output from the board. I am sending a square wave to
the audio port, but there is no audio output. What am I doing wrong
here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

There is no point in downloading to a chip before you have simulated
the code. Have you run a simulation?


Rick,

If your entire code consists of a 16-bit up counter with
reset, do you really need to simulate it? My guess is that
the code does exactly what he expects. It's something outside
the coding / simulation environment (i.e. board level pin
assignment and circuitry) that is screwing up.

Why should he not simulate it? The guy starts his post saying, "I am
learning verilog".

Simulation is much easier to do than loading it into a board and yes,
there are any number of coding mistakes to be made, even for a simple
resetable counter.

BTW, I doubt the problem is any filtering on the output. If he is
expecting to hear the output that would imply any filtering is for audio
signals and with a divisor of 2^16 even a 50 MHz clock will produce a
tone below 1 kHz.

--

Rick

 

[GaborSzakacs]

Maj55 wrote:

I am learning verilog using a Nexys 4 board. I have written the code below for audio output from the board. I am sending a square wave to the audio port, but there is no audio output. What am I doing wrong here?

`timescale 1ns / 1ps
module soundtest(
input clk,
input hush,
input [3:0] note,
output ampPWM, //speaker port
output vcc,
reg [15:0] counter //binary counter; 16 bits wide
);
// The audio amplifier needs to be enabled, by
// default it will be disabled without this:
localparam TCQ = 1;

always @ (posedge clk or negedge hush)
if ( hush == 1'b0)
counter <= 'b0;
else
counter <= counter + 1;

assign ampPWM = counter[15];

endmodule

Taking another look, you have an output called "vcc" which has
no driver. Was your intent to tie this high? Also there is
a localparam TCQ that isn't used. The comment above it suggests
that there should be some code which uses this parameter and
that code is involved in turning on the amplifier.

--
Gabor

 

[Maj55]

I reviewed and modified my code and able to have an audio output from my board.

Here is the modified code:

`timescale 1ns / 1ps
module soundtest (
input clk,
input hush,
input [3:0] note,
output ampPWM,
output vcc
);

localparam TCQ = 1;
assign vcc = 1'b1;

reg [15:0] counter;
reg ampPWM;

always @(posedge clk)
begin
if(counter == 53628) //rounded half period clck cycle count for desired freq
begin
counter <= 0;
ampPWM <= ~ampPWM;
end
else
counter <= counter+1;
end

endmodule

 

Hi Maja! Could you tell me please where did you find this info:
"The audio amplifier needs to be enabled, by

// default it will be disabled without this:
localparam TCQ = 1;"

I think I read carefully (maybe not) the user manual, and I'm in the middle of some project that need the audio output I haven't reach that last step (almost, I'm at the PWM) of sending the signal to the speaker, but, I would like to know...where you find that information?
Thanks!