Attribute that shows if signal is clocked or not?

[Colin Beighley]

Hello,

Is there a VHDL attribute that tells whether or not a signal is driven
synchronously or asynchronously? I have found a place in my design
where I think a latch would be nice to use, but I'd like to have some
sort of assert statement like the following to make sure it isn't
driven asynchronously.

assert latch_enable'synchronous
report "Latch enable must be a synchronous signal to avoid
glitches"
severity failure;

Thanks,
Colin

 

[KJ]

On Jul 20, 10:17 pm, Colin Beighley <colinbeigh...@gmail.com> wrote:

Hello,

Is there a VHDL attribute that tells whether or not a signal is driven
synchronously or asynchronously?

No

I have found a place in my design
where I think a latch would be nice to use,

If this is targetting an FPGA, then check to make sure that the target
device actually has a latch primitive. If not, then the synthesis
tool will implement the latch with logic and you'll likely find that
using a latch is not so nice after all.

Even if the FPGA *does* have latches, you'll have to manually check to
see that the implemented design actually does use the latch primitive
rather than cobbling it together with logic cells.

but I'd like to have some
sort of assert statement like the following to make sure it isn't
driven asynchronously.

Sound like you're into generating internal clock-like signsls...if the
target device is an FPGA you'll likely regret this decision. Data
hold timing will bite you.

Kevin Jennings

 

[Gabor]

KJ wrote:

On Jul 20, 10:17 pm, Colin Beighley <colinbeigh...@gmail.com> wrote:
Hello,

Is there a VHDL attribute that tells whether or not a signal is driven
synchronously or asynchronously?

No

I have found a place in my design
where I think a latch would be nice to use,

If this is targetting an FPGA, then check to make sure that the target
device actually has a latch primitive. If not, then the synthesis
tool will implement the latch with logic and you'll likely find that
using a latch is not so nice after all.

Even if the FPGA *does* have latches, you'll have to manually check to
see that the implemented design actually does use the latch primitive
rather than cobbling it together with logic cells.

but I'd like to have some
sort of assert statement like the following to make sure it isn't
driven asynchronously.


Sound like you're into generating internal clock-like signsls...if the
target device is an FPGA you'll likely regret this decision. Data
hold timing will bite you.

Kevin Jennings

Regardless of your target, most synthesis tools will warn when you
create latches. I haven't seen any that allow you to promote a
latch warning to an error, but you can always grep the synthesis
report to see if any latch warnings were generated. I'm sure
that reading through the warnings after synthesis is a useful
exercise anyway...

-- Gabor