attribute +generate statement

chris · Feb 10, 2004

Hi, I'm trying to used the primitive 
ROM128X1 in my design and I want to initialise the attribute INIT of this primitive. 
This is working fine when I use only one primitive like : ---------------------------- 
architecture ... component ROM128X1 
&nbsp;-- synthesis translate_off 
&nbsp;generic (INIT : bit_vector := X"128"); 
&nbsp;-- synthesis translate_on 
&nbsp;port ( 
&nbsp;&nbsp;&nbsp;&nbsp;O : out std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A0 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A1 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A2 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A3 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A4 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A5 : in std_ulogic; 
&nbsp;&nbsp;&nbsp;&nbsp;A6 : in std_ulogic 
&nbsp

; 
&nbsp;end component; attribute INIT : string; 
attribute INIT of U : label is ".."; begin 
&nbsp;&nbsp;&nbsp;&nbsp;U : ROM128X1 
&nbsp;&nbsp;&nbsp;&nbsp;port map( 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;O => data_out, 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A0 => addr_in(0), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A1 => addr_in(1), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A2 => addr_in(2), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A3 => addr_in(3), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A4 => addr_in(4), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A5 => addr_in(5), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A6 => addr_in(6) 
&nbsp;&nbsp;&nbsp;&nbsp

; 
end; 
---------------------------- but in the case I used a generate statement like : ---------------------------- 
begin 
&nbsp;&nbsp;&nbsp;&nbsp;t : for i in 0 to 1 generate 
&nbsp;&nbsp;&nbsp;&nbsp;U : ROM128X1 
&nbsp;&nbsp;&nbsp;&nbsp;port map( 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;O => data_out(i), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A0 => addr_in(0), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A1 => addr_in(1), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A2 => addr_in(2), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A3 => addr_in(3), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A4 => addr_in(4), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A5 => addr_in(5), 
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;A6 => addr_in(6) 
&nbsp;&nbsp;&nbsp;&nbsp

; 
&nbsp;&nbsp;&nbsp;&nbsp;end generate; 
end; 
--------------------------- what name of instance do I have to use to declare the attributes INIT. Thanks

Barry Brown · Feb 11, 2004

Something like U_0 and U_1, but I believe it depends on your synthesis tool.
Check your synthesis output for the correct labels.

"chris" <ccoutand@hotmail.com> wrote in message
news:ee82713.-1@WebX.sUN8CHnE...
Hi,
I'm trying to used the primitive
ROM128X1 in my design and I want to initialise the attribute INIT of this
primitive.
This is working fine when I use only one primitive like :
----------------------------
architecture ...
component ROM128X1
-- synthesis translate_off
generic (INIT : bit_vector := X"128");
-- synthesis translate_on
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic
);
end component;
attribute INIT : string;
attribute INIT of U : label is "..";
begin
U : ROM128X1
port map(
O => data_out,
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end;
----------------------------
but in the case I used a generate statement like :
----------------------------
begin
t : for i in 0 to 1 generate
U : ROM128X1
port map(
O => data_out(i),
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end generate;
end;
---------------------------
what name of instance do I have to use to declare the attributes INIT.
Thanks

Francisco Rodriguez · Feb 11, 2004

Hi

It's easier to embed the attribute inside the generate
and assign the attribute value using some kind of function
to make the code portable. Something like

t: for i in 0 to 1 generate
attribute INIT of U: label is rom_init_values(i);
begin
U: ROM128X1 port map (
xxxx );
end generate;

where you've previously declared a constant array of init values for your
ROMs.
You can even put that constant array inside the generate, just before the
attribute line

Best regards
Francisco Rodriguez

"Barry Brown" <barry_brown@remove_this.agilent.com> escribió en el mensaje
news:1076520492.769192@cswreg.cos.agilent.com...

Something like U_0 and U_1, but I believe it depends on your synthesis
tool.
Check your synthesis output for the correct labels.

"chris" <ccoutand@hotmail.com> wrote in message
news:ee82713.-1@WebX.sUN8CHnE...
Hi,
I'm trying to used the primitive
ROM128X1 in my design and I want to initialise the attribute INIT of this
primitive.
This is working fine when I use only one primitive like :
----------------------------
architecture ...
component ROM128X1
-- synthesis translate_off
generic (INIT : bit_vector := X"128");
-- synthesis translate_on
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic
);
end component;
attribute INIT : string;
attribute INIT of U : label is "..";
begin
U : ROM128X1
port map(
O => data_out,
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end;
----------------------------
but in the case I used a generate statement like :
----------------------------
begin
t : for i in 0 to 1 generate
U : ROM128X1
port map(
O => data_out(i),
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end generate;
end;
---------------------------
what name of instance do I have to use to declare the attributes INIT.
Thanks

Ray Andraka · Feb 11, 2004

the naming of elements built by a generate statement is not
specified by the LRM, and is not consistent from tool to
tool. To make it portable, as well as easier on yourself,
put the attribute in the generate statement declaration
rather than outside. Also, you'll need to specify the value
for the generic with a generic map so that simulation
matches the hardware:

----------------------------

architecture ...

component ROM128X1
-- synthesis translate_off
generic (INIT : bit_vector := X"128");
-- synthesis translate_on
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic
);
end component;

attribute INIT : string;

begin
t : for i in 0 to 1 generate

attribute INIT of U:label is "..";

U : ROM128X1

generic map(
INIT => "...")

port map(
O => data_out(i),
A0 => addr_in(0),
A1 => addr_in(1),
A2 => addr_in(2),
A3 => addr_in(3),
A4 => addr_in(4),
A5 => addr_in(5),
A6 => addr_in(6)
);
end generate;
end;

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759

attribute +generate statement

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