Attempting to run I2S protocol in SystemVerilog: error in te

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Otto Hunt

Guest
This is my first post to this group. Here goes!

I was fortunate to find verilog I2S code here: https://github.com/skristiansson/i2s

I converted this Verilog code to SystemVerilog. I got the transmit and receive files to compile in Quartus, but I cannot get the (converted) testbench to compile in ModelSim PE Altera edition. I also tried running it at EDA Playground here: http://www.edaplayground.com/x/Jz9 and got similar errors that were even more cryptic.

The error in ModelSim is:

-- Compiling module i2s_tb
** Error: C:/Users/Otto/Google Drive/engineering/verilog/I2S_xmit/I2S_xmit_rtl/i2s_tb.sv(3): near "parameter": syntax error, unexpected parameter, expecting ')'

This has got to be a simple error that I am just not seeing. I would appreciate if someone else would take a minute to (probably instantly) point out this error to me. Thanks.
 
On Monday, March 23, 2015 at 5:18:55 AM UTC-7, gabor wrote:
Otto Hunt wrote:
This is my first post to this group. Here goes!

I was fortunate to find verilog I2S code here: https://github.com/skristiansson/i2s

I converted this Verilog code to SystemVerilog. I got the transmit and receive files to compile in Quartus, but I cannot get the (converted) testbench to compile in ModelSim PE Altera edition. I also tried running it at EDA Playground here: http://www.edaplayground.com/x/Jz9 and got similar errors that were even more cryptic.

The error in ModelSim is:

-- Compiling module i2s_tb
** Error: C:/Users/Otto/Google Drive/engineering/verilog/I2S_xmit/I2S_xmit_rtl/i2s_tb.sv(3): near "parameter": syntax error, unexpected parameter, expecting ')'

This has got to be a simple error that I am just not seeing. I would appreciate if someone else would take a minute to (probably instantly) point out this error to me. Thanks.

Any chance you can post the offending lines? It sounds like you left
out a comma.

--
Gabor
OK, here it is:
Click to expand...

timeunit 1ns;
timeprecision 1ns;
module i2s_tb (parameter AUDIO_DW = 16)(

input logic lrclk;
input logic sdata;
input logic [AUDIO_DW-1:0] left_tx_chan;
input logic [AUDIO_DW-1:0] right_tx_chan;
input logic [AUDIO_DW-1:0] left_rx_chan;
input logic [AUDIO_DW-1:0] right_rx_chan;
input logic sclk = 1'b1;
input logic rst = 1'b1;
);
always #5 sclk <= ~sclk;
initial #100 rst = 0;
 
Otto Hunt wrote:
This is my first post to this group. Here goes!

I was fortunate to find verilog I2S code here: https://github.com/skristiansson/i2s

I converted this Verilog code to SystemVerilog. I got the transmit and receive files to compile in Quartus, but I cannot get the (converted) testbench to compile in ModelSim PE Altera edition. I also tried running it at EDA Playground here: http://www.edaplayground.com/x/Jz9 and got similar errors that were even more cryptic.

The error in ModelSim is:

-- Compiling module i2s_tb
** Error: C:/Users/Otto/Google Drive/engineering/verilog/I2S_xmit/I2S_xmit_rtl/i2s_tb.sv(3): near "parameter": syntax error, unexpected parameter, expecting ')'

This has got to be a simple error that I am just not seeing. I would appreciate if someone else would take a minute to (probably instantly) point out this error to me. Thanks.
Click to expand...

Any chance you can post the offending lines? It sounds like you left
out a comma.

--
Gabor
 
On Monday, March 23, 2015 at 9:07:18 AM UTC-7, Otto Hunt wrote:
OK, here it is:

module i2s_tb (parameter AUDIO_DW = 16)(

input logic lrclk;
....
input logic sclk = 1'b1;
input logic rst = 1'b1;
);
Click to expand...

This has nothing to do with SystemVerilog. This isn't legal regular Verilog.

1) for list of ports, items end with commas, not semicolons.
2) last item (rst) shouldn't have any comma or semicolon at end.

module i2s_tb (parameter AUDIO_DW = 16)(
input logic lrclk,
input logic sdata,
input logic [AUDIO_DW-1:0] left_tx_chan,
input logic [AUDIO_DW-1:0] right_tx_chan,
input logic [AUDIO_DW-1:0] left_rx_chan,
input logic [AUDIO_DW-1:0] right_rx_chan,
input logic sclk = 1'b1,
input logic rst = 1'b1
);

Have you used Verilog much? ANSI-style port declarations have been around since Verilog-2001.

David
 
unfrostedpoptart wrote:
On Monday, March 23, 2015 at 9:07:18 AM UTC-7, Otto Hunt wrote:
OK, here it is:

module i2s_tb (parameter AUDIO_DW = 16)(

input logic lrclk;
....
input logic sclk = 1'b1;
input logic rst = 1'b1;
);

This has nothing to do with SystemVerilog. This isn't legal regular Verilog.

1) for list of ports, items end with commas, not semicolons.
2) last item (rst) shouldn't have any comma or semicolon at end.

module i2s_tb (parameter AUDIO_DW = 16)(
input logic lrclk,
input logic sdata,
input logic [AUDIO_DW-1:0] left_tx_chan,
input logic [AUDIO_DW-1:0] right_tx_chan,
input logic [AUDIO_DW-1:0] left_rx_chan,
input logic [AUDIO_DW-1:0] right_rx_chan,
input logic sclk = 1'b1,
input logic rst = 1'b1
);

Have you used Verilog much? ANSI-style port declarations have been around since Verilog-2001.

David
Click to expand...

You forgot the first error:

module i2s_tb (parameter AUDIO_DW = 16)(

should read:

module i2s_tb #(parameter AUDIO_DW = 16)(

The "#" indicates a parameter block instead of the module ports.

--
Gabor
 
On Monday, March 23, 2015 at 1:17:15 PM UTC-7, gabor wrote:
unfrostedpoptart wrote:
On Monday, March 23, 2015 at 9:07:18 AM UTC-7, Otto Hunt wrote:
OK, here it is:

module i2s_tb (parameter AUDIO_DW = 16)(

input logic lrclk;
....
input logic sclk = 1'b1;
input logic rst = 1'b1;
);

This has nothing to do with SystemVerilog. This isn't legal regular Verilog.

1) for list of ports, items end with commas, not semicolons.
2) last item (rst) shouldn't have any comma or semicolon at end.

module i2s_tb (parameter AUDIO_DW = 16)(
input logic lrclk,
input logic sdata,
input logic [AUDIO_DW-1:0] left_tx_chan,
input logic [AUDIO_DW-1:0] right_tx_chan,
input logic [AUDIO_DW-1:0] left_rx_chan,
input logic [AUDIO_DW-1:0] right_rx_chan,
input logic sclk = 1'b1,
input logic rst = 1'b1
);

Have you used Verilog much? ANSI-style port declarations have been around since Verilog-2001.

David

You forgot the first error:

module i2s_tb (parameter AUDIO_DW = 16)(

should read:

module i2s_tb #(parameter AUDIO_DW = 16)(

The "#" indicates a parameter block instead of the module ports.

--
Gabor
Click to expand...

A big thankyou to Gabor and unfrostedpoptart for the help. That simulation file does compile now. I have been studying Verilog, then SystemVerilog for about five months, and it is still a bit iffy in that I still need a little hand holding. Just for kicks, here is the file that ModelSim thinks is hunkydory:

timeunit 1ns;
timeprecision 1ns;
module i2s_tb #(parameter AUDIO_DW = 16);

logic lrclk;
logic sdata;
logic [AUDIO_DW-1:0] left_tx_chan;
logic [AUDIO_DW-1:0] right_tx_chan;
wire [AUDIO_DW-1:0] left_rx_chan;
wire [AUDIO_DW-1:0] right_rx_chan;
logic sclk = 1'b1;
logic rst = 1'b1;

always #5 sclk <= ~sclk;
initial #100 rst = 0;

i2s_tx #(.AUDIO_DW (AUDIO_DW))
i2s_tx0 (
.sclk (sclk),
.rst (rst),

.prescaler (16'd16),

.lrclk (lrclk),
.sdata (sdata),

.left_chan (left_tx_chan),
.right_chan (right_tx_chan)
);
i2s_rx #(.AUDIO_DW (AUDIO_DW))
i2s_rx0 (
.sclk (sclk),
.rst (rst),

.lrclk (lrclk),
.sdata (sdata),

.left_chan (left_rx_chan),
.right_chan (right_rx_chan)
);
initial begin
left_tx_chan = 16'h0123;
right_tx_chan = 16'habcd;
@(negedge rst);
@(posedge lrclk);
@(negedge lrclk);
@(posedge sclk);
@(negedge sclk);
if (left_rx_chan == left_tx_chan && right_rx_chan == right_tx_chan)
$display("Test passed!");
else
$display("Test failed!");
#100 $finish();
end

endmodule
 
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