Atmel WinCupl

[Paul K]

I am very new to PAL programming. I have created a few to decode
addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.

I now need to latch data appearing on 3 inputs when a certain
condition is met on 3 other inputs.

I need to latch the data on a cpu data buss D0, D1, & D2 when the
signal write (WR\) is low, and the signal chip enable (CE\) is low and
the signal output enable (OE\)is high, then latch the data on D0-D3.

I currently have the circuit working with a 74LS02 (NOR)with the
inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
(AND)the other input is tied to OE\. The output of the AND gate feeds
a 73LS273 latch. I will be latching on the falling edge of WR\

I don't have room for the 3 TTL chips so I am trying to move it to the
16V8.

I am not sure how to approach the latch, any help or push in the right
direction would be greatly appreciated. I have had a hard time
finding examples using the latching feature.

Thanks, Paul

 

[Jim Granville]

Paul K wrote:

I am very new to PAL programming. I have created a few to decode
addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.

I now need to latch data appearing on 3 inputs when a certain
condition is met on 3 other inputs.

I need to latch the data on a cpu data buss D0, D1, & D2 when the
signal write (WR\) is low, and the signal chip enable (CE\) is low and
the signal output enable (OE\)is high, then latch the data on D0-D3.

I currently have the circuit working with a 74LS02 (NOR)with the
inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
(AND)the other input is tied to OE\. The output of the AND gate feeds
a 73LS273 latch. I will be latching on the falling edge of WR\

I don't have room for the 3 TTL chips so I am trying to move it to the
16V8.

I am not sure how to approach the latch, any help or push in the right
direction would be greatly appreciated. I have had a hard time
finding examples using the latching feature.

Here is an example, of a HC259 adr latch, minus the field statements
QL = DV & WrQ /* Follow */
# !WrQ & Qfb /* Hold */
# Qfb & DV /* Overlap */
# Reset /* Reset Forces all HI -> All OFF */
;

This is a change-over MUX, but the key line is the overlap one, you need
a MAKE-before-break MUX.

An alterative if you are not pushed for pins, is to flip the WRN using
PLD resource, hard wire that to the CLK pin,
and then use WR rising edge to clock std D 16V8 registers

QL.d = Update & Di
# !Update & QL;
-jg

 

[Mike Harrison]

On 14 Jun 2004 18:38:54 -0700, accrg@accrepairs.com (Paul K) wrote:

I am very new to PAL programming. I have created a few to decode
addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.

I now need to latch data appearing on 3 inputs when a certain
condition is met on 3 other inputs.

I need to latch the data on a cpu data buss D0, D1, & D2 when the
signal write (WR\) is low, and the signal chip enable (CE\) is low and
the signal output enable (OE\)is high, then latch the data on D0-D3.

I currently have the circuit working with a 74LS02 (NOR)with the
inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
(AND)the other input is tied to OE\. The output of the AND gate feeds
a 73LS273 latch. I will be latching on the falling edge of WR\

I don't have room for the 3 TTL chips so I am trying to move it to the
16V8.

I am not sure how to approach the latch, any help or push in the right
direction would be greatly appreciated. I have had a hard time
finding examples using the latching feature.

Thanks, Paul

My CUPL is a little rusty so excuse any punctuation errors...

pin[2..5] = [d0..3];
pin[12..15] = [q0..3];
pin[6,7,8] = [!ce,!oe,!wr];

field din=[d0..3];
field dout=[q0..3];

enable = !CE & OE & !WR;

dout = !enable & dout /* hold latch contents by feeding output back to input */
# enable & din;

 

[Paul K]

Thanks Mike and Jim for the replies, I will go off and digest this and
see what happens. This is also the first time I have used the groups,
thank you very much for the replies.

Paul


Mike Harrison <mike@whitewing.co.uk> wrote in message news:<t7ftc0l7fj5fqu89qpgpri2btgfntnciis@4ax.com>...

On 14 Jun 2004 18:38:54 -0700, accrg@accrepairs.com (Paul K) wrote:

I am very new to PAL programming. I have created a few to decode
addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.

I now need to latch data appearing on 3 inputs when a certain
condition is met on 3 other inputs.

I need to latch the data on a cpu data buss D0, D1, & D2 when the
signal write (WR\) is low, and the signal chip enable (CE\) is low and
the signal output enable (OE\)is high, then latch the data on D0-D3.

I currently have the circuit working with a 74LS02 (NOR)with the
inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
(AND)the other input is tied to OE\. The output of the AND gate feeds
a 73LS273 latch. I will be latching on the falling edge of WR\

I don't have room for the 3 TTL chips so I am trying to move it to the
16V8.

I am not sure how to approach the latch, any help or push in the right
direction would be greatly appreciated. I have had a hard time
finding examples using the latching feature.

Thanks, Paul

My CUPL is a little rusty so excuse any punctuation errors...

pin[2..5] = [d0..3];
pin[12..15] = [q0..3];
pin[6,7,8] = [!ce,!oe,!wr];

field din=[d0..3];
field dout=[q0..3];

enable = !CE & OE & !WR;

dout = !enable & dout /* hold latch contents by feeding output back to input */
# enable & din;

 

[Paul K]

Mike
I started off using your code, it looks more like what I am used to
using.

I am not clear on the feeding back of the output to the input. This
is done internal to the PAL?

I fixed an upper/lower case problem, the enable line was uppercase and
pins 6,7,8 were lower. Now I am getting a 0014CB error,

"The variable used as an input was previously assigned to an output
that is neither bidirectional nor feeds back into the input array."

My device is g16v8a, when I do a device independant compile it seems
happier, I guess because it doesn't know the pins (input vrs output)
of my device independant device.

Here is the code I am compiling now.........

pin[2..5] = [D0..3];
pin[6,7,8] = [!ce,!oe,!wr];

pin[12..15] = [Q0..3];


field din=[D0..3];
field dout=[Q0..3];

enable = !ce & oe & !wr;

dout = !enable & dout /* hold latch contents by feeding output back
to input */
# enable & din;

WHAT I THINK I UNDERSTAND.........
So, we are first saying pins 2, 3, 4, 5 will be known as D0, D1, D2, &
D3
next we say pins 12, 13, 15, & 15 will be outputs Q0, Q1, Q2, & Q3.
next, pin 6 is chip enable active low, pin 7, is output enable active
low, and pin 8 is assigned write not active low.
we say DIN is the data inputs D0-D3 and DOUT is Q0-Q3.

When we are active CE is low, OE is high, and WR is low.

NOW FOR THE FUN PART........
DOUT is equal to when not enabled ANDed with DOUT ORed with enabled
and the data in?

NOT SURE I GET THAT ONE.......

Thanks all again for your support,

Paul K.


accrg@accrepairs.com (Paul K) wrote in message news:<a5ad9202.0406151436.22f4fdfb@posting.google.com>...

Thanks Mike and Jim for the replies, I will go off and digest this and
see what happens. This is also the first time I have used the groups,
thank you very much for the replies.

Paul


Mike Harrison <mike@whitewing.co.uk> wrote in message news:<t7ftc0l7fj5fqu89qpgpri2btgfntnciis@4ax.com>...
On 14 Jun 2004 18:38:54 -0700, accrg@accrepairs.com (Paul K) wrote:

I am very new to PAL programming. I have created a few to decode
addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.

I now need to latch data appearing on 3 inputs when a certain
condition is met on 3 other inputs.

I need to latch the data on a cpu data buss D0, D1, & D2 when the
signal write (WR\) is low, and the signal chip enable (CE\) is low and
the signal output enable (OE\)is high, then latch the data on D0-D3.

I currently have the circuit working with a 74LS02 (NOR)with the
inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
(AND)the other input is tied to OE\. The output of the AND gate feeds
a 73LS273 latch. I will be latching on the falling edge of WR\

I don't have room for the 3 TTL chips so I am trying to move it to the
16V8.

I am not sure how to approach the latch, any help or push in the right
direction would be greatly appreciated. I have had a hard time
finding examples using the latching feature.

Thanks, Paul

My CUPL is a little rusty so excuse any punctuation errors...

pin[2..5] = [d0..3];
pin[12..15] = [q0..3];
pin[6,7,8] = [!ce,!oe,!wr];

field din=[d0..3];
field dout=[q0..3];

enable = !CE & OE & !WR;

dout = !enable & dout /* hold latch contents by feeding output back to input */
# enable & din;