ATMEL support / Are they serious ?

F

Fred Bartoli

Guest
Hello,

I've designed in an instrument board an ATMEL CPLD.
For that purpose I had to use their "low cost" software.
First I tried the CUPL tool, but it was too much bugged. Then I used their
VHDL "prochip designer" which is based on altium tool and their proprietary
fitters.
After some fighting with VHDL (my first project) I finally had it all OK
with simulation, synthesis and fitting (PAR). I had to work around some
strange synthesizer results but finally got it OK.

Then came the time of timing analysis, using the vital files provided by
their fitter.
Again some annoying bugs, like (traced by comparing the vital/edif/fitter
equations report files)
- generated vital files not compatible with their provided vital library
(quickly derived from their fpga library)
- some vital outputs with the wrong polarity
- some floating vital CPLD internal signals
- some *strange* results like DFFs with permanent reset, or permanently
disabled CE...

OK, so far I think (I've not tested the CPLD as I still don't have the
board) I know where the errors are in their outputs and that my final design
is OK.

I've made a *nice* bug report to ATMEL with all my analysis, my commented
sources, their file results, and all that's needed to help them quickly
reproduce the bugs, and also an enquiry about whether my analysis and
consequently my jedec output files were good or not.
All that sent, as requested, to their pld support 2 weeks ago. I had no
acknowledge, no answer, not even an evidence of live, despite one reminder a
few days ago.

Are these guys serious ?
Any experience ?

Thanks,
Fred.
 
"Fred Bartoli"
<fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote in
message news:40714abb$0$19461$626a14ce@news.free.fr...
Hello,

I've designed in an instrument board an ATMEL CPLD.
For that purpose I had to use their "low cost" software.
First I tried the CUPL tool, but it was too much bugged. Then I used their
VHDL "prochip designer" which is based on altium tool and their
proprietary
fitters.
After some fighting with VHDL (my first project) I finally had it all OK
with simulation, synthesis and fitting (PAR). I had to work around some
strange synthesizer results but finally got it OK.

Then came the time of timing analysis, using the vital files provided by
their fitter.
Again some annoying bugs, like (traced by comparing the vital/edif/fitter
equations report files)
- generated vital files not compatible with their provided vital library
(quickly derived from their fpga library)
- some vital outputs with the wrong polarity
- some floating vital CPLD internal signals
- some *strange* results like DFFs with permanent reset, or permanently
disabled CE...

OK, so far I think (I've not tested the CPLD as I still don't have the
board) I know where the errors are in their outputs and that my final
design
is OK.

I've made a *nice* bug report to ATMEL with all my analysis, my commented
sources, their file results, and all that's needed to help them quickly
reproduce the bugs, and also an enquiry about whether my analysis and
consequently my jedec output files were good or not.
All that sent, as requested, to their pld support 2 weeks ago. I had no
acknowledge, no answer, not even an evidence of live, despite one reminder
a
few days ago.
Click to expand...
I've always found Xilinx and Altera support very good for their CPLDs and
FPGAs. Perhaps you are using the wrong chips. :cool:

Leon
 
"Leon Heller" <leon_heller@hotmail.com> a écrit dans le message news:
407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com...
snip
Click to expand...

I've always found Xilinx and Altera support very good for their CPLDs and
FPGAs. Perhaps you are using the wrong chips. :cool:
Click to expand...
Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ?
Too bad Xilinx threw away the 5V Coolrunner parts.

Plus the ATMEL "logic doubling" is a nice thing that allow me to pack my
design in a 64MC-TQFP44 device instead of a 128MC. The board is pretty dense
and have no room
for 128MC which would've made mandatory a much bigger (to me) 80-100 pin
package.

Thanks,
Fred.
 
Fred Bartoli wrote:
Hello,

I've designed in an instrument board an ATMEL CPLD.
For that purpose I had to use their "low cost" software.
First I tried the CUPL tool, but it was too much bugged. Then I used their
VHDL "prochip designer" which is based on altium tool and their proprietary
fitters.
After some fighting with VHDL (my first project) I finally had it all OK
with simulation, synthesis and fitting (PAR). I had to work around some
strange synthesizer results but finally got it OK.

Then came the time of timing analysis, using the vital files provided by
their fitter.
Again some annoying bugs, like (traced by comparing the vital/edif/fitter
equations report files)
- generated vital files not compatible with their provided vital library
(quickly derived from their fpga library)
- some vital outputs with the wrong polarity
- some floating vital CPLD internal signals
- some *strange* results like DFFs with permanent reset, or permanently
disabled CE...

OK, so far I think (I've not tested the CPLD as I still don't have the
board) I know where the errors are in their outputs and that my final design
is OK.

I've made a *nice* bug report to ATMEL with all my analysis, my commented
sources, their file results, and all that's needed to help them quickly
reproduce the bugs, and also an enquiry about whether my analysis and
consequently my jedec output files were good or not.
All that sent, as requested, to their pld support 2 weeks ago. I had no
acknowledge, no answer, not even an evidence of live, despite one reminder a
few days ago.

Are these guys serious ?
Any experience ?
Click to expand...
CUPL has a number of component pieces. The low level compiler and
functional simulator certainly have some quirks, but these are
predictable, stable, and easily avoided.
The CUPL shell we avoid, instead using a std Pgmr Editor, and the
command line compiler.
When working on designs near the ceiling, much of the effort is
in check/control of the fitter, and CUPL is better at low level
control than VHDL is.
Timing simulations I would not sweat too much over with a CPLD,
you can always use a calculator and the fitter report, to check
some 'key suspect paths'.
The fitter is the same in both flows.
-jg
 
Paul Carpenter wrote:

On Monday, in article
4071836c$0$14178$636a15ce@news.free.fr
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo
"Fred Bartoli" wrote:


"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news:
407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com...

snip

I've always found Xilinx and Altera support very good for their CPLDs and
FPGAs. Perhaps you are using the wrong chips. :cool:


Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ?
Too bad Xilinx threw away the 5V Coolrunner parts.


I know too well about that demise, but it was on the cards when Xilinx
bought out Philips Coolrunner. I personally prefer the old Philips tools for
Coolrunners over the Webpack (your own 100baseT connection to Xilinx server
for the downloads required).
Click to expand...
Lattice claim 5V tolerant I/O on their new LC4xxx family, but they do
need multiple supplies.
-jg
 
On Monday, in article
<4071836c$0$14178$636a15ce@news.free.fr>
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo
"Fred Bartoli" wrote:

"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news:
407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com...

snip

I've always found Xilinx and Altera support very good for their CPLDs and
FPGAs. Perhaps you are using the wrong chips. :cool:


Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ?
Too bad Xilinx threw away the 5V Coolrunner parts.
Click to expand...
I know too well about that demise, but it was on the cards when Xilinx
bought out Philips Coolrunner. I personally prefer the old Philips tools for
Coolrunners over the Webpack (your own 100baseT connection to Xilinx server
for the downloads required).

--
Paul Carpenter | paul@pcserv.demon.co.uk
<http://www.pcserv.demon.co.uk/> Main Site
<http://www.gnuh8.org.uk/> GNU H8 & mailing list info.
<http://www.badweb.org.uk/> For those web sites you hate.
 
Jim Granville wrote:
Paul Carpenter wrote:

On Monday, in article
4071836c$0$14178$636a15ce@news.free.fr
fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo
"Fred Bartoli" wrote:


"Leon Heller" <leon_heller@hotmail.com> a ?crit dans le message news:
407153a3$0$3300$cc9e4d1f@news-text.dial.pipex.com...

snip

I've always found Xilinx and Altera support very good for their CPLDs and
FPGAs. Perhaps you are using the wrong chips. :cool:


Well, does Xilinx/Altera have a *low* power *5V* CPLD offer ?
Too bad Xilinx threw away the 5V Coolrunner parts.


I know too well about that demise, but it was on the cards when Xilinx
bought out Philips Coolrunner. I personally prefer the old Philips tools for
Coolrunners over the Webpack (your own 100baseT connection to Xilinx server
for the downloads required).

Lattice claim 5V tolerant I/O on their new LC4xxx family, but they do
need multiple supplies.
Click to expand...
They do have a 3.3 volt only version that just uses one supply, however
it is not "zero" power.

As to the 5 volt tolerance, Read the fine print carefully. The Lattice
parts have a max number of IOs that can be above 3.3 volts at the same
time.

I ended up using an Altera EP1K part which is fully 5 volt tolerant even
with the power off. But of course it is RAM based, not Flash. MCU
anyone?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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