Asynchrous reset.

[One Day & A Knight]

Hi, there:

I am a little confused with Asynchronous set/reset...
The Synopsys manual said:
A clock or an asynchronous preload condition. For example,
always @ ( posedge CLOCK or negedge reset ) begin
if !reset begin
.... statements ...
end
else begin
.... statements ...
end
end

In my RTL codes I wrote:
always @ (posedge clk_fdiv_in or negedge sd_en_in)
begin
if (sd_en_in == 1'b0)
r_sumout1 <= 16'h0000;
else
r_sumout1 <= sumout1;
end

In my simulation, I defined
initial
begin
clk_fdiv <= 1'b0;
sd_en <= 1'b0;
// #5 sd_en <= 1'b0;
#25 sd_en <= 1'b1;
end


HOW COME:

In the simulation result, the register value is 16'h0000 at time 0 even if I
don't have the falling edge on sd_en_in...

Can anybody explain this behavor?

Finally after synthesis, will the reset pin of all the flip-flops be "level
sentsitive" or falling-edge sensitive?

Best Regards,
Kelvin

 

[Muzaffer Kal]

On Fri, 21 Nov 2003 17:34:33 +0800, "One Day & A Knight"
<kelvin8157@hotmail.com> wrote:

Hi, there:

I am a little confused with Asynchronous set/reset...
The Synopsys manual said:
A clock or an asynchronous preload condition. For example,
always @ ( posedge CLOCK or negedge reset ) begin
if !reset begin
... statements ...
end
else begin
... statements ...
end
end

In my RTL codes I wrote:
always @ (posedge clk_fdiv_in or negedge sd_en_in)
begin
if (sd_en_in == 1'b0)
r_sumout1 <= 16'h0000;
else
r_sumout1 <= sumout1;
end

In my simulation, I defined
initial
begin
clk_fdiv <= 1'b0;
sd_en <= 1'b0;
// #5 sd_en <= 1'b0;
#25 sd_en <= 1'b1;
end


HOW COME:

In the simulation result, the register value is 16'h0000 at time 0 even if I
don't have the falling edge on sd_en_in...

Can anybody explain this behavor?

Finally after synthesis, will the reset pin of all the flip-flops be "level
sentsitive" or falling-edge sensitive?

Best Regards,
Kelvin

Actually there is a falling edge as the initial value of sd_en_in is X
and you assign 0 to it at time 0 and X->0 is defined as a falling edge
transition.
After synthesis, reset pin as defined above will be a level sensitive
reset without the need for a clock.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations