asynchronous counter synthesis

[RobertG]

Hello,

I have a *behavioral* description of a 7 bit counter. I would like to make
it asynchronous (ripple counter) but everytime I run synthesis I get
synchronous type, where all flip-flops' clock inputs share the same
clock signal. I use BuildGates v05.14 as a synthesis tool.
How can I make BuildGates to generate an asynchronous structure? I
cannot/don't want to use structural description.
Thank you for any information.
Regards,
Robert

 

[m]

On Tue, 17 Jan 2006 00:10:36 +0900, RobertG <robert@nec.example.net>
wrote:

Hello,

I have a *behavioral* description of a 7 bit counter. I would like to make
it asynchronous (ripple counter) but everytime I run synthesis I get
synchronous type, where all flip-flops' clock inputs share the same
clock signal. I use BuildGates v05.14 as a synthesis tool.
How can I make BuildGates to generate an asynchronous structure? I
cannot/don't want to use structural description.

BG is certainly not smart enough to change your async counter to a
sync one. How are you coding the ripple counter ? If you want the
clock of one flop to be the output of a previous flop then you have to
code it that way. If you post your code it would help in helping you.

 

[RobertG]

On Mon, 16 Jan 2006 18:46:52 +0000, mk wrote:

On Tue, 17 Jan 2006 00:10:36 +0900, RobertG <robert@nec.example.net
wrote:

BG is certainly not smart enough to change your async counter to a
sync one. How are you coding the ripple counter ? If you want the
clock of one flop to be the output of a previous flop then you have to
code it that way. If you post your code it would help in helping you.

Hello,

I want to achieve opposite than you describe above, from synchronous
style (by default BG synthesizes to synchronous counter) to asynchronous.
And my code is very basic, you can imagine it as something like the
following for instance:

always @(posedge clk)
begin
count <= count + 7'b1;
...
end

Now, I think it is not possible to achieve it without hardcoding the
actual connections (wires) so using structural style. But maybe BG has
some options for synthesizing this into ripple counter. Anyway, thank you
for the answer.

Robert

 

[m]

On Wed, 18 Jan 2006 00:26:55 +0900, RobertG <robert@nec.example.net>
wrote:

On Mon, 16 Jan 2006 18:46:52 +0000, mk wrote:

On Tue, 17 Jan 2006 00:10:36 +0900, RobertG <robert@nec.example.net
wrote:

BG is certainly not smart enough to change your async counter to a
sync one. How are you coding the ripple counter ? If you want the
clock of one flop to be the output of a previous flop then you have to
code it that way. If you post your code it would help in helping you.

Hello,

I want to achieve opposite than you describe above, from synchronous
style (by default BG synthesizes to synchronous counter) to asynchronous.
And my code is very basic, you can imagine it as something like the
following for instance:

always @(posedge clk)
begin
count <= count + 7'b1;
...
end

Now, I think it is not possible to achieve it without hardcoding the
actual connections (wires) so using structural style. But maybe BG has
some options for synthesizing this into ripple counter. Anyway, thank you
for the answer.

Robert

I am not sure I understand your terminology. As far as I am concerned,
a ripple counter is one which is made of full adders where carry
"ripples" slowly through every adder. You can get one if you constrain
your clock with a low enough period. There is nothing "asynchronous"
about a ripple counter. I thought you meant a ripple divider where
flops are connected so that the output of one flops goes to the clock
input of the next and output of each flop is connected to its input
too. This is useful for a frequency divider usually. Maybe you should
explain your problem in more detail.

 

[Paul Muller]

Hello,

I want to achieve opposite than you describe above, from synchronous
style (by default BG synthesizes to synchronous counter) to asynchronous.
And my code is very basic, you can imagine it as something like the
following for instance:

always @(posedge clk)
begin
count <= count + 7'b1;
...
end

Hi

Your description is sensitive to the positive clock edge, i.e. it is a
synchronous description. If you want an asynchronous counter, start with
an asynchronous description. I am not familiar with BG, but it would
certainly respect the properties of your description and not "invent"
some synchronicity.

Paul

 

[RobertG]

I will answer both posts from you and Paul.

Put "ripple counter" into google and click the first link it pops up
with. Or use the following:
http://www.eelab.usyd.edu.au/digital_tutorial/part2/counter02.html

If you look at the waveforms in the picture you can see that the output
bits change from 00 to 11 with the clock yet it is called asynchronous
counter. This is what I want to achieve.

Thanks for replies.

 

[m]

On Wed, 18 Jan 2006 23:18:07 +0900, RobertG <robert@nec.example.net>
wrote:

I will answer both posts from you and Paul.

Put "ripple counter" into google and click the first link it pops up
with. Or use the following:
http://www.eelab.usyd.edu.au/digital_tutorial/part2/counter02.html

If you look at the waveforms in the picture you can see that the output
bits change from 00 to 11 with the clock yet it is called asynchronous
counter. This is what I want to achieve.

Thanks for replies.

This is what I described in my post ie the output of a flop is
connected to the clock input of the next flop. When you say "always
@(posedge clk)" you are describing a structure where all the clock
inputs of all flops are connected to "clk". If you want a structure
where all flops have different clocks (ie the ouput of the previous
flop), you need to code it that way. BG will not change your code at
the very least because it has no idea what you want.