V
Vips
Guest
Hi Everyone,
I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.
The motoroll Processor will have LBC Local bus controller signals will
be comunicating to my interface inside the FPGA.
The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.
I have to design an interface where the control signals from the
processor to my interface will be
1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase. (From processor to Design )
2. LWE it is a read and write signal single bit active low. (From
processor to Design )
3. LOE Output enable active low (From processor to Design )
4. LCS is active low signal from processor to my interface. It is used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor to Design )
6. LAD data 32 bits (Bidirectional)
I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .
I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .
My Confusion is that when we have multiple control signal passing the
clock domain . Can we synchronize with 2 flops all the control
signals.
Shall we use some glue logic to make sure we pass and synchronise only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that are
input to a latch and sampled when we get the synchronized signal.
In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.
I am using 3X clock in the destination clock domain and has ample time
to sample the signal in the interface block.
Any suggestion ideas will be highly appreciated
Thanks
Vipul
I am designing a system where I am interfacing a Motorolla processor
in my system for read and write data. This processor is on the board
where my fpga will interact with it. The processor is the master mode
always and the salave is my interface design and the fpga.
The motoroll Processor will have LBC Local bus controller signals will
be comunicating to my interface inside the FPGA.
The processor can run at configurable clock of 33 MHz to 133 MHz. The
address bus is 24 Bits and tye data bus is 32 bits.
I have to design an interface where the control signals from the
processor to my interface will be
1. LALE Used for latching address and making is two distict phases as
data and address phase. The LALE when HIgh is an Address phase and
when Address is low it is Data phase. (From processor to Design )
2. LWE it is a read and write signal single bit active low. (From
processor to Design )
3. LOE Output enable active low (From processor to Design )
4. LCS is active low signal from processor to my interface. It is used
for selecting the chip/slave chip select
5. LA address 24 bits ( From processor to Design )
6. LAD data 32 bits (Bidirectional)
I am thinking about runing my design at 300 Mhx 3X then the processor
LBC clock . The LBC clock is not coming from the processor to my
interface in fpga . So in my Interface i dont have the reference clock
from the processor and all the above mentioned signals are from
Processor to my design except LAD which is bidirectional .
I am using 2 flop synchronisers for the control signals and MUX-Latch
model for data latching and synchronization across the cock domain .
My Confusion is that when we have multiple control signal passing the
clock domain . Can we synchronize with 2 flops all the control
signals.
Shall we use some glue logic to make sure we pass and synchronise only
one control signal across the domain and later use this synchronous
signal value to select the mux-latch of other control signals that are
input to a latch and sampled when we get the synchronized signal.
In the scenario like this has anyone used multiple control signals to
pass the clock domain throgh individual 2 flop synchronizers for each
control lines.
I am using 3X clock in the destination clock domain and has ample time
to sample the signal in the interface block.
Any suggestion ideas will be highly appreciated
Thanks
Vipul