Asynchcronous clear, sorta

[Jesper]

I'm trying to play around with Xilinx CPLD and make a simple frequency
counter.

I'm trying to do this :
--------------------------

always @(posedge reset)
q <= 0;

always @(posedge clk)
begin
q <= q + 1;
end

------------------------

But get an error about Multi-Source on q bla bla

I understand WHY I get the error, but I don't see how I should write
this to avoid the problem.

clk is the unknown frequency input and reset is a 1 second signal from
the timebase. There's a little more to it that this, but it illustrates
the problem.

I cannot have both reset and clk in the same "always" and do "if
(reset)", because the reset need to be on the flank of the reset signal,
not on the level.

Any help to a confused noob much apreciated.

 

[John_H]

always @(posedge clk or posedge reset)
if( reset ) q <= 0;
else q <= q+1;

The syntheis and simulation will both provide a reset that's valid on both
the reset edge *and* the "flank" or level. If you want a *synchronous*
reset that resets the count on the first valid clock edge that reset is
high, then it would be

always @(posedge clk)
if( reset ) q <= 0;
else q <= q+1;

It might not have *looked* like the reset would stay active during the
successive clock edges, but the always block is entered with the posedge clk
and the reset is active so the counter stays reset. It's clean.


"Jesper" <jesperh@telia.com> wrote in message
news:ICd5f.36284$d5.193193@newsb.telia.net...

I'm trying to play around with Xilinx CPLD and make a simple frequency
counter.

I'm trying to do this :
--------------------------

always @(posedge reset)
q <= 0;

always @(posedge clk)
begin
q <= q + 1;
end

------------------------

But get an error about Multi-Source on q bla bla

I understand WHY I get the error, but I don't see how I should write this
to avoid the problem.

clk is the unknown frequency input and reset is a 1 second signal from the
timebase. There's a little more to it that this, but it illustrates the
problem.

I cannot have both reset and clk in the same "always" and do "if (reset)",
because the reset need to be on the flank of the reset signal, not on the
level.

Any help to a confused noob much apreciated.

 

[John_H]

Sorry - I just understood the use of the "flank" term.

If you want the reset to apply at the rising edge but then allow counting on
successive clock edges, you should change your reset to an edge detector.
Register the reset twice with clk. If the once-registered reset is high and
the twice-registered reset is low, reset the counter. This edge detector &
synchronizer is necessary to keep the reset from being seen in some places
but not others on a single clock edge.


"John_H" <johnhandwork@mail.com> wrote in message
news:Nle5f.28$9O6.385@news-west.eli.net...

always @(posedge clk or posedge reset)
if( reset ) q <= 0;
else q <= q+1;

The syntheis and simulation will both provide a reset that's valid on both
the reset edge *and* the "flank" or level. If you want a *synchronous*
reset that resets the count on the first valid clock edge that reset is
high, then it would be

always @(posedge clk)
if( reset ) q <= 0;
else q <= q+1;

It might not have *looked* like the reset would stay active during the
successive clock edges, but the always block is entered with the posedge
clk and the reset is active so the counter stays reset. It's clean.


"Jesper" <jesperh@telia.com> wrote in message
news:ICd5f.36284$d5.193193@newsb.telia.net...

I'm trying to play around with Xilinx CPLD and make a simple frequency
counter.

I'm trying to do this :
--------------------------

always @(posedge reset)
q <= 0;

always @(posedge clk)
begin
q <= q + 1;
end

------------------------

But get an error about Multi-Source on q bla bla

I understand WHY I get the error, but I don't see how I should write this
to avoid the problem.

clk is the unknown frequency input and reset is a 1 second signal from
the timebase. There's a little more to it that this, but it illustrates
the problem.

I cannot have both reset and clk in the same "always" and do "if
(reset)", because the reset need to be on the flank of the reset signal,
not on the level.

Any help to a confused noob much apreciated.

 

[Jesper]

The problem lies partly in that the clk signal not really is a "clock".
It's the input to the counter, which may be very slow.
Anyway, what I really wanted was to be able to use a 1Hz signal to gate
the count, but that caused a 1 second wait on the other half period.
I wanted to reset and start counting on the edge of the timing reference.
I'm still new to this, and have some trouble realizing that you cant
just write any code in verilog as you would in C ;-)
There has to be support in the HW for it.

I solved it like with a temporary counter variable like this :

initial flag = 0;

always @(posedge clk)
begin
if (en != flag) // if the level has flipped
begin
q <= q1; // set count on outputs
q1 = 1; // 1 as this is already the first count
flag <= en; // flip flag
end
q1 <= q1 + 1; // count
end



John_H wrote:

Sorry - I just understood the use of the "flank" term.

If you want the reset to apply at the rising edge but then allow counting on
successive clock edges, you should change your reset to an edge detector.
Register the reset twice with clk. If the once-registered reset is high and
the twice-registered reset is low, reset the counter. This edge detector &
synchronizer is necessary to keep the reset from being seen in some places
but not others on a single clock edge.


"John_H" <johnhandwork@mail.com> wrote in message
news:Nle5f.28$9O6.385@news-west.eli.net...

always @(posedge clk or posedge reset)
if( reset ) q <= 0;
else q <= q+1;

The syntheis and simulation will both provide a reset that's valid on both
the reset edge *and* the "flank" or level. If you want a *synchronous*
reset that resets the count on the first valid clock edge that reset is
high, then it would be

always @(posedge clk)
if( reset ) q <= 0;
else q <= q+1;

It might not have *looked* like the reset would stay active during the
successive clock edges, but the always block is entered with the posedge
clk and the reset is active so the counter stays reset. It's clean.


"Jesper" <jesperh@telia.com> wrote in message
news:ICd5f.36284$d5.193193@newsb.telia.net...

I'm trying to play around with Xilinx CPLD and make a simple frequency
counter.

I'm trying to do this :
--------------------------

always @(posedge reset)
q <= 0;

always @(posedge clk)
begin
q <= q + 1;
end

------------------------

But get an error about Multi-Source on q bla bla

I understand WHY I get the error, but I don't see how I should write this
to avoid the problem.

clk is the unknown frequency input and reset is a 1 second signal from
the timebase. There's a little more to it that this, but it illustrates
the problem.

I cannot have both reset and clk in the same "always" and do "if
(reset)", because the reset need to be on the flank of the reset signal,
not on the level.

Any help to a confused noob much apreciated.