Async FIFO code

[Nathaniel]

hey,
I am doing a pretty cool project using processors working on different
clock domains on the same FPGA. For com purposes, i need an async fifo,
but i cannot use the logic Core fifo's from xilinx or altera, we wan
the design platform-independant. Is there any good source code in
VHDL/Verilog for an asynchronous FIFO?

Nathaniel

 

asynchronous FIFO?
Do you mean a FIFO with asynchronous clear or a FIFO with

unsynchronized read and write clocks?

 

[Nathaniel]

a FIFO with async read and write clocks

 

There is some example shown on
"www.vhdl-online.de"
model lib patras.

Haven't tested it but have a look at it. Maybe some inspiration ...

Rgds
André

 

[Nathaniel]

thanks a milion
i'll check to see if it's half decent and report back

NA