A
Assura User
Guest
I am trying to extract a logic path (e.g. a critical path) in the
layout to perform detailed spice simulations on it. The path would
start at a pin/net and end at another pin/net, and it will contain a
bunch of logic gates (std cells) between the input and output pins.
After going through the assura userguide, it appears to me that the
path tracing (expansion) algorithm would stop when it encounters a MOS
gate. How is it possible to extract the entire logic path consisting of
several logic gates and nets?
Would appreciate your comments
Best regards
Saby.
layout to perform detailed spice simulations on it. The path would
start at a pin/net and end at another pin/net, and it will contain a
bunch of logic gates (std cells) between the input and output pins.
After going through the assura userguide, it appears to me that the
path tracing (expansion) algorithm would stop when it encounters a MOS
gate. How is it possible to extract the entire logic path consisting of
several logic gates and nets?
Would appreciate your comments
Best regards
Saby.