Assura parasitic capacitance probe

Hi,

When I extract my layout including the parasitic caps, I get a bunch
of caps from each net, floating around in the layout.

My question is, how can I find where exactly these capacitors come
from? in other words, lets say I get two parasitic capacitors between
nodes /out and /outb with values 5 fF and 0.1 fF. I'd like to know
where the 5-fF capacitor is generated from and from which parts of the
layout; so I can get more insight in reducing those.

thanks a lot!

-Ali

 

[Mobil]

On Sep 27, 9:09 am, alip.u...@gmail.com wrote:

Hi,

When I extract my layout including the parasitic caps, I get a bunch
of caps from each net, floating around in the layout.

My question is, how can I find where exactly these capacitors come
from? in other words, lets say I get two parasitic capacitors between
nodes /out and /outb with values 5 fF and 0.1 fF. I'd like to know
where the 5-fF capacitor is generated from and from which parts of the
layout; so I can get more insight in reducing those.

thanks a lot!

-Ali

Open schematic view, then Launch (IC6.1.1) -> parasitic -> setup...
(setup with your extract view) -Report parasitic

 

[alip]

On Sep 29, 1:54 am, Mobil <mobil...@gmail.com> wrote:

On Sep 27, 9:09 am, alip.u...@gmail.com wrote:

Hi,

When I extract my layout including the parasitic caps, I get a bunch
of caps from each net, floating around in the layout.

My question is, how can I find where exactly these capacitors come
from? in other words, lets say I get two parasitic capacitors between
nodes /out and /outb with values 5 fF and 0.1 fF. I'd like to know
where the 5-fF capacitor is generated from and from which parts of the
layout; so I can get more insight in reducing those.

thanks a lot!

-Ali

Open schematic view, then Launch (IC6.1.1) -> parasitic -> setup...
(setup with your extract view) -Report parasitic

Thanks for the reply. In this way, I can see all the parasitic
capacitance associated with that node. My question is to find where
each of these capacitors belong to in the layout. In other words, I
like to know what metal layers (fringe or area) produce each of these
capacitors.

-Ali

 

[Riad KACED]

Dear Ali,

This steps are from my IC 5141, I don't know about IC6.

1. Run LVS/RCX
2. Open the RCX extracted View
3. Go to Tools -> Parasitics. This will add the Parasitics menu to
your VLE.
4. Launch Parasitics -> Setup and fill the required data for cross
probing
5. Launch Parasitics -> Report Parasitics -> Net
6. Select a net from your schematic. A Parasitics form pops up. It
display all the R/C/L/K/ parasitics related to that net.
7. Click any line in this from, Lets say the one that shows /c1. By
clicking this line, your RCX window is getting zoomed to the c1 symbol
and it does highlight all the layers that made this c1. Just play
around with the zoom to seem the whole picture.

For more information about this probing the parasitics, please give a
look at
the VirtuosoŽ Parasitic Simulation User Guide; parasim.pdf in your IC
stream.

Hope this helps,
Riad.

 

[alip]

Thanks Riad,

That's exactly what I was looking for. Now I can get a sense of where
my caps are coming from.

thanks for the help

-Ali