Assura LVS question

[Adam]

Dear All,

I got some questions about Assura LVS. In the LVS debug window,
I selected "compare", there shows "Devices, 6" which means there are
six mismatched devices. Then I clicked "open tool", there are 5
devices
in the schematic side, and 1 device in the layout side. However, when
I
selected one of the devices in the schematic side, and clicked
"probe",
there is this message shown in CIW:

\a _vuiMismatchViewCB("Devices" "probe" 'sch)
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\o Removed Probe for schematic device:/XI0_1, no mapping to layout
device
\w *WARNING* Object XI0_1 does not exist in VCO CC10_v6 schematic
\o Probed schematic device:/XI0_1, no mapping to layout device
\r t

If I select a device in the layout list, and clicked "probe", CIW
shows:


\a _vuiLayInfoSelectCB("Devices")
\r nil
\a vuiDevicesMismatchForm->layInfoBox->value = '("avD2769_1
(nfet_rf)" )
\r ("avD2769_1 (nfet_rf)")
\a _vuiLayInfoSelectCB("Devices")
\r nil
\a _vuiMismatchViewCB("Devices" "probe" 'lay)
\o Removed Probe for layout device:/avD2769_1, no mapping to schematic
device
\o Probed layout device:/avD2769_1, no mapping to schematic device
\r t
\a hiResizeWindow(window(1) list(61:200 1168:454))
\r t

Anybody know the reason?

Thanks in advance,

Adam

 

On Feb 11, 5:11 am, Adam <wang.adam2...@gmail.com> wrote:

Dear All,

I got some questions about Assura LVS. In the LVS debug window,
I selected "compare", there shows "Devices, 6" which means there are
six mismatched devices. Then I clicked "open tool", there are 5
devices
in the schematic side, and 1 device in the layout side. However, when
I
selected one of the devices in the schematic side, and clicked
"probe",
there is this message shown in CIW:

\a _vuiMismatchViewCB("Devices" "probe" 'sch)
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\w *WARNING* Pattern "XI0_1" not found.
\o Removed Probe for schematic device:/XI0_1, no mapping to layout
device
\w *WARNING* Object XI0_1 does not exist in VCO CC10_v6 schematic
\o Probed schematic device:/XI0_1, no mapping to layout device
\r t

If I select a device in the layout list, and clicked "probe", CIW
shows:

\a _vuiLayInfoSelectCB("Devices")
\r nil
\a vuiDevicesMismatchForm->layInfoBox->value = '("avD2769_1
(nfet_rf)" )
\r ("avD2769_1 (nfet_rf)")
\a _vuiLayInfoSelectCB("Devices")
\r nil
\a _vuiMismatchViewCB("Devices" "probe" 'lay)
\o Removed Probe for layout device:/avD2769_1, no mapping to schematic
device
\o Probed layout device:/avD2769_1, no mapping to schematic device
\r t
\a hiResizeWindow(window(1) list(61:200 1168:454))
\r t

Anybody know the reason?

Thanks in advance,

Adam

Hi Adam,
I'm no expert but judging from the info. regarding number of device
mismatch, could it be due to the difference in parameter of your n-
transistor fingers?
Have you compared the w & l of the transistor in the schematic with
the one in the layout?
Is the compare function working as expected for rf transistors?

I-FAB

 

On Feb 11, 10:08 am, cop0...@gmail.com wrote:

Hi Adam,
I'm no expert but judging from the info. regarding number of device
mismatch, could it be due to the difference in parameter of your n-
transistor fingers?
Have you compared the w & l of the transistor in the schematic with
the one in the layout?
Is the compare function working as expected for rf transistors?

I-FAB

Hi,

I mistook your warnings with something else I previously had (which
was early last year).
My problems were due to either (1) wrong definition in the binding
file or (2) wrong device terminal definitions - and they occured on
fixed devices (I don't think an rf transistor instance would be
created as a fixed pcell).
Now, I'm intrigued by the "Pattern ..." warning (as well as the number
of its occurence). Is the device type supposed to be recognised by
text (you would need to check extraction method of the transistor)?
How about try setting avParameter option for the LVS run: ?
abortOnMissingSchematic to t? It might indicate whether the problem
was during extraction of schematic device.
Is there any other helpful message in Assura's generated files
(i.e. .log or .msg files)?
Usually Assura's generated files reveal more details although sifting
through them can be overwhelming even for the simplest errors.

Sorry for the too generic response.

I-FAB

 

[Adam]

Hi I-FAB,

Thank you for your detailed message. As you mentioned, I got
the .log file which is below:

Thanks again,

Adam




Assura (tm) Physical Verification Version
av3.1roduction:dfII5.1.41-64b:5.10.41-64b.500.3.31
Release 317_USR2_HF10

Copyright (c) Cadence Design Systems. All rights reserved.
@(#)$CDS: assura_64 version av3.1roduction:dfII5.1.41-64b:
5.10.41-64b.500.3.31 07/10/2008 02:03 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653

run on...


Starting ...
@(#)$CDS: aveng_64 version av3.1roduction:dfII5.1.41-64b:5.10.41-64b.
500.3.31 07/10/2008 02:03 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653

run on .....

rcGlobalInit
Summary Report: CC10_v6.sum

RSF : /...../RF/CC10_v6.rsf
Library Name : VCO
CDSLIB Path : "/.../cds.lib"
Cell Name : CC10_v6
View Name : layout
Rules File : /...IBM9RF/IBM_PDK/cms9flp/relIBM/Assura/QRC/
5_01_00_01_LD/extract.rul
Options : -gui -exec1 -LVS -cdslib /.../cds.lib
Work Directory: .
Operating Mode: Legacy Mode is Off
Increased use of dataReduction is On
New hierarchical select is On


Starting dfIIToVdb...
@(#)$CDS: dfIIToVdb_64 version av3.1roduction:dfII5.1.41-64b:
5.10.41-64b.500.3.31 07/10/2008 02:04 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653

run on ...

rcGlobalInit
Loading IBM A&MS cms9flp Procedures for Cadence Version

"av3.1roduction:dfII5.1.41-64b:5.10.41-64b.500.3.31"
Compiling rules...

warn: rcReadTextFile: cannot read textFile "add_text.file".
warn: LVS Run detected.
Non-legacy mode has been disabled for this LVS run
Checking out license for Assura_DRC 3.10

Reading the design data...



Finished dfIIToVdb.

Building the VDB part 2 in background mode.

Building tables for LVS Preprocessing in background mode.


Starting /.../cadence/assura317/tools/assura/bin/vdbToCells . CC10_v6

Finished /.../cadence/assura317/tools/assura/bin/vdbToCells

Starting Nvn PreExtraction...

Starting .../cadence/assura317/tools/assura/bin/nvn /.../CC10_v6.rsf -
preExtract -exec1 -cdslib /home/hd00/l/lwang04/RF/cds.lib
@(#)$CDS: nvn_64 version av3.1roduction:dfII5.1.41-64b:5.10.41-64b.
500.3.31 07/10/2008 02:05 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653
run on.....
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
dioDevice("havar" ("PLUS" "MINUS" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("dgdtcap" ("PLUS" "MINUS" nil))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("mimcap" ("HT" "QT" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("mimhk" ("HK" "QK" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("vncap" ("IN" "OUT" "SUB"))

.......
.......

function parSubcont redefined
function INDcomp redefined
*WARNING* the rule 'filter' has been converted into 'filterOptions'
with the same function.
*WARNING* bindingFile - 'if(' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'avSwitch(' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'resimulate_extracted' is not a valid keyword
on line 14. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'then' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 43.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'if(' is not a valid keyword on line 44.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - '!avSwitch(' is not a valid keyword on line
44. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'resimulate_extracted' is not a valid keyword
on line 44. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 44.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'then' is not a valid keyword on line 44.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 73.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
Reading schematic network
inputting netlist /..../CC10_v6.netlist.lvs
*WARNING* *.EQUATION is not supported
*WARNING* *.MEGA is not supported
*WARNING* *.PIN is not supported
*WARNING* duplicate subckt name: symindp in /../CC10_v6.netlist.lvs
line:135
The old subckt definition will be erased
*WARNING* duplicate subckt name: esdvpnp in /../CC10_v6.netlist.lvs
line:161
The old subckt definition will be erased
*WARNING* duplicate subckt name: esdndsx in /../CC10_v6.netlist.lvs
line:174
The old subckt definition will be erased
*WARNING* duplicate subckt name: bondpad in /../CC10_v6.netlist.lvs
line:187
The old subckt definition will be erased
*WARNING* The capability to discard or ignore devices is not available
Therefore all devices were included in the output
Even though no *.BIPOLAR command was found
Reading layout network
inputting network CC10_v6.ldb
*WARNING* bindingFile/bind rule - schematic cell 'NFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'NFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'hvtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'hvtnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'hvtnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'svtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'svtnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'svtnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfettw4_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'NFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'NFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'hvtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'hvtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'hvtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'svtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'svtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'svtnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFETTW_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfettw_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'hvtnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'hvtpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'HVTPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgdtcap' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgdtcap' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'DGDTCAP' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgdtcap' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNCAP' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'ADNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'ADNFETTW' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'ADPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGNFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGPFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgvnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgxnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgvnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVNFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgxnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXNFET_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgvpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgxpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgvpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGVPFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'dgxpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'DGXPFET_RF' is not
found.
*WARNING* bindingFile/bind rule - layout cell 'dgxpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'svtnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'svtpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'SVTPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'EFUSE' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'subc' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'SUBC' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'ESDNDSX' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'ESDVNPN' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'ESDVPNP' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'fuse' is not found.
*WARNING* bindingFile/bind rule - layout cell 'fuse' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'FUSE' is not found.
*WARNING* bindingFile/bind rule - layout cell 'fuse' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'havar' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'HAVAR' is not found.
*WARNING* bindingFile/bind rule - schematic cell 'BONDPAD' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvspadres' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVSPADRES' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvsres' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVSRES' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvtnfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvtnfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTNFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvtpfet' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTPFET' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'lvtpfet_rf' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'LVTPFET_RF' is not
found.
*WARNING* bindingFile/bind rule - schematic cell 'mimcap' is not
found..


.........

Preprocessing schematic network phase 1
*WARNING* dioDevice - cell 'havar' not found.
*WARNING* capDevice - cell 'mimhk' not found.
*WARNING* capDevice - cell 'mimcap' not found.
*WARNING* genericDevice("subc") - cell does not exist. This command
will be ignored.
*WARNING* genericDevice("svtnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("hvtnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("pcap") - cell does not exist. This command
will be ignored.
*WARNING* genericDevice("ncap") - cell does not exist. This command
will be ignored.
*WARNING* genericDevice("dgncap") - cell does not exist. This command
will be ignored.
*WARNING* setPower - cell 'vdd!' is not found.
*WARNING* setGround - cell 'gnd!' is not found.
Preprocessing layout network phase 1
Preprocessing schematic network phase 2
Preprocessing layout network phase 2
cpu=0.00m wall=0.03m mem=33.20mb

Finished /.../cadence/assura317/tools/assura/bin/nvn
*WARNING* '?expandCellToParent' list: No cell name match for kxres*
*WARNING* '?expandCellToParent' list: No cell name match for havar*
*WARNING* '?expandCellToParent' list: No cell name match for zvt*
*WARNING* '?expandCellToParent' list: No cell name match for vncap*
*WARNING* '?expandCellToParent' list: No cell name match for vpnp*
*WARNING* '?expandCellToParent' list: No cell name match for tdpdnw*
*WARNING* '?expandCellToParent' list: No cell name match for tdndsx*
*WARNING* '?expandCellToParent' list: No cell name match for subc*
*WARNING* '?expandCellToParent' list: No cell name match for
singlewire*
*WARNING* '?expandCellToParent' list: No cell name match for
singlecpw*
*WARNING* '?expandCellToParent' list: No cell name match for
sblkndres*
*WARNING* '?expandCellToParent' list: No cell name match for silres*
*WARNING* '?expandCellToParent' list: No cell name match for mimhk*
*WARNING* '?expandCellToParent' list: No cell name match for mimcap*
*WARNING* '?expandCellToParent' list: No cell name match for hvtpfet*
*WARNING* '?expandCellToParent' list: No cell name match for hvtnfet*
*WARNING* '?expandCellToParent' list: No cell name match for lvtpfet*
*WARNING* '?expandCellToParent' list: No cell name match for lvtnfet*
*WARNING* '?expandCellToParent' list: No cell name match for svtpfet*
*WARNING* '?expandCellToParent' list: No cell name match for svtnfet*
*WARNING* '?expandCellToParent' list: No cell name match for rfline*
*WARNING* '?expandCellToParent' list: No cell name match for ind*

.........


uilding the VDB part 3 in background mode.

Finished building the VDB. VDB build times for main process:
cpu: 0.63 elap: 27 pf: 0 in: 0 out: 0 virt: 69M phys: 0M

Running the Task Processor, 8 cells, 15474 steps...

Top Cell is 'CC10_v6 layout VCO'

Executing: bkgnd = geomBkgnd()

Executing: tw = geomOr(tw1 n3 geomAndNot(t3 nw))

Executing: ca = geomOr(CA_drawing)

Executing: v1 = geomOr(V1_drawing)

Executing: v2 = geomOr(V2_drawing)

Executing: v3 = geomOr(V3_drawing)


........

inished running rules. Task processor time in main process:
cpu: 7.53 elap: 14 pf: 0 in: 0 out: 0 virt: 125M phys: 0M

No output post-processing: This is not a DRC run

Finished building the persistent database.
cpu: 0.02 elap: 0 pf: 0 in: 0 out: 0 virt: 125M phys: 0M


***** aveng terminated normally *****


Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/aveng

Starting /Linux/sw/request/cadence/assura317/tools/assura/bin/avrpt /
home/hd00/l/lwang04/RF/CC10_v6.rsf
@(#)$CDS: avrpt_64 version av3.1roduction:dfII5.1.41-64b:5.10.41-64b.
500.3.31 07/10/2008 02:04 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653

run on haldir.ecs.syr.edu from /Linux/sw/request/cadence/assura317/
tools.lnx86/assura/bin/64bit/avrpt on Wed Feb 11 14:30:14 2009


Creating Error Database 'CC10_v6'...

Reading VDB ...
--------------------------------------------------------------------------------
Rule Message FlatCount
RealCount
--------------------------------------------------------------------------------
( 1) dataAuditErrors
0 0
( 2) (PC lvsres) not covered by mask PC
0 0
( 3) (NW lvsres) not covered by mask NW
0 0
( 4) ESD NW containing RX outside ESD
0 0
( 5) VPNP NW touching RX outside VPNP
0 0
( 6) havar cathode touching BP
0 0
( 7) havar cathode N+ not inside NW
0 0
( 8) havar anode touching NW
0 0
( 9) havar NW extending beyond device
0 0
( 10) havar NW shorting to triple well nBand
0 0
( 11) HAVAR NW touching RX outside HAVAR
0 0
( 12) NCAP device missing nw
0 0
( 13) ncap device touching lvt,hvt,ZVT,pd,op
0 0
( 14) ncap device PC touching an external RX
0 0
( 15) NCAP NW touching an additional N+ diffus
1 1
( 16) PCAP device not inside T3/N3,BP
0 0
( 17) pcap device PC touching an external RX
0 0
( 18) pcap device touching hvt,ZVT,pd,op
0 0
( 19) Dual gate poly device without M1/CA conn
0 0
( 20) NFET gate touching PD
0 0
( 21) N+ Diffused Resistor device touching dg,
0 0
( 22) opndres and s>1 with internal m1 strap c
0 0
( 23) opndres and s>1 with internal m1 strap c
0 0
( 24) PFET gate touching PD
0 0
( 25) Polysilicon Resistor device touching rx,
0 0
( 26) Polysilicon Resistor device without BP
0 0
( 27) opndres and s>1 with internal m1 strap c
0 0
( 28) opndres and s>1 with internal m1 strap c
0 0
( 29) silres and s>1 with internal m1 strap co
0 0
( 30) (LD lvsres) not covered by mask LD
0 0
( 31) (OL lvsres) not covered by mask OL
0 0
( 32) (M1_2B lvsres) not covered by mask M1_2B
0 0
( 33) (M5 lvsres) not covered by mask M5
0 0
( 34) (M4 lvsres) not covered by mask M4
0 0
( 35) (M3 lvsres) not covered by mask M3
0 0
( 36) (M2 lvsres) not covered by mask M2
0 0
( 37) (M1 lvsres) not covered by mask M1
0 0
( 38) KXRES and s>1 with internal M1_2B strap
0 0
( 39) Copper MIM HT not connected by mask jt
0 0
( 40) Copper MIM QT not connected by mask JT
0 0
( 41) HighK MIM HK not connected by mask JT
0 0
( 42) HighK MIM QK not connected by mask JT
0 0
( 43) M1_2B signal wire not exiting transmissi
0 0
( 44) M5 signal wire not exiting transmission
0 0
( 45) M4 signal wire not exiting transmission
0 0
( 46) M3 signal wire not exiting transmission
0 0
( 47) M2 signal wire not exiting transmission
0 0
( 48) M1 signal wire not exiting waveGuide lin
0 0
( 49) LD signal wire not exiting transmission
0 0
( 50) OL signal wire not exiting transmission
0 0
( 51) pwell_StampErrorConnect
0 0
( 52) pwell_StampErrorFloat
0 0
( 53) pwell_StampErrorMult
0 0
( 54) nw_StampErrorConnect
0 0
( 55) nw_StampErrorFloat
0 0
( 56) nw_StampErrorMult
0 0
( 57) substrate_StampErrorCon
1 1
( 58) inductor_BF_substrate_StampErrorCon
0 0
( 59) bondpad_BF_substrate_StampErrorCon
0 0
( 60) bondpad_RX_substrate_StampErrorCon
0 0
( 61) nBand_StampErrorCon
0 0
( 62) ###### Seven 5&2 Cu metal M1-M2-M3-M4-M5
25 8
( 63) malformed device kx_dev
0 0
( 64) malformed device KXRES_sbar
0 0
( 65) malformed device KXRES_pbar
0 0
( 66) malformed device coupledCPWD
0 0
( 67) malformed device singleCPWD
0 0
( 68) malformed device coupledCPWO
0 0
( 69) malformed device singleCPWO
0 0
( 70) malformed device coupledCPW12b
0 0
( 71) malformed device singleCPW12b
0 0
( 72) malformed device coupledCPW5
0 0
( 73) malformed device singleCPW5
0 0
( 74) malformed device coupledCPW4
0 0
( 75) malformed device singleCPW4
0 0
( 76) malformed device coupledCPW3
0 0
( 77) malformed device singleCPW3
0 0
( 78) malformed device coupledCPW2
0 0
( 79) malformed device singleCPW2
0 0
( 80) malformed device coupledCPW1
0 0
( 81) malformed device singleCPW1
0 0
( 82) unstable device for ld_RES_Device_10077
0 0
( 83) unstable device for pad_RES_Device_10074
0 0
( 84) unstable device for ol_RES_Device_10071
0 0
( 85) unstable device for m1_2b_RES_Device_100
0 0
( 86) unstable device for m5_RES_Device_10063
0 0
( 87) unstable device for m4_RES_Device_10059
0 0
( 88) unstable device for m3_RES_Device_10056
0 0
( 89) unstable device for m2_RES_Device_10050
0 0
( 90) unstable device for m1_RES_Device_10044
0 0
( 91) unstable device for nw_RES_Device_10041
0 0
( 92) unstable device for pc_RES_Device_10035
0 0
( 93) unstable device for efuse_Device_10032
0 0
( 94) unstable device for ESD_VNPN_comp_Device
0 0
( 95) unstable device for ESD_VNPN_Device_9956
0 0
( 96) unstable device for ESD_VPNP_Device_9949
0 0
( 97) unstable device for ESD_NDSX_Device_9942
0 0
( 98) unstable device for ESD_NDSX_comp_Device
0 0
( 99) unstable device for bondPrx_Device_9829
0 0
( 100) unstable device for bondPbf_Device_9822
0 0
( 101) unstable device for bondPm1_Device_9815
0 0
( 102) unstable device for bondPrxC4_Device_980
0 0
( 103) unstable device for bondPbfC4_Device_980
0 0
( 104) unstable device for bondPm1C4_Device_979
0 0
( 105) unstable device for SYMIND_OL_M5_m1m
0 0
( 106) unstable device for SYMIND_OL_M5_m1p
0 0
( 107) unstable device for SYMIND_OL_M5_bf
0 0
( 108) unstable device for SYMIND_OL_M5_pw
0 0
( 109) unstable device for SYMIND_OL_M5_sx
0 0
( 110) unstable device for SYMIND_OL_m1m
0 0
( 111) unstable device for SYMIND_OL_m1p
0 0
( 112) unstable device for SYMIND_OL_bf
0 0
( 113) unstable device for SYMIND_OL_pw
0 0
( 114) unstable device for SYMIND_OL_sx
0 0
( 115) unstable device for SYMINDP_OL_M5_m1m
0 0
( 116) unstable device for SYMINDP_OL_M5_m1p
0 0
( 117) unstable device for SYMINDP_OL_M5_bf
0 0
( 118) unstable device for SYMINDP_OL_M5_pw
0 0
( 119) unstable device for SYMINDP_OL_M5_sx
0 0
( 120) unstable device for SYMINDP_OL_m1m
0 0
( 121) unstable device for SYMINDP_OL_m1p
0 0
( 122) unstable device for SYMINDP_OL_bf
0 0
( 123) unstable device for SYMINDP_OL_pw
0 0
( 124) unstable device for SYMINDP_OL_sx
0 0
( 125) unstable device for SYMIND_LD_M12B_m1m
0 0
( 126) unstable device for SYMIND_LD_M12B_m1p
0 0
( 127) unstable device for SYMIND_LD_M12B_bf
0 0
( 128) unstable device for SYMIND_LD_M12B_pw
0 0
( 129) unstable device for SYMIND_LD_M12B_sx
0 0
( 130) unstable device for SYMIND_LD_m1m
0 0
( 131) unstable device for SYMIND_LD_m1p
0 0
( 132) unstable device for SYMIND_LD_bf
0 0
( 133) unstable device for SYMIND_LD_pw
0 0
( 134) unstable device for SYMIND_LD_sx
0 0
( 135) unstable device for SYMINDP_LD_M12B_m1m
0 0
( 136) unstable device for SYMINDP_LD_M12B_m1p
0 0
( 137) unstable device for SYMINDP_LD_M12B_bf
0 0
( 138) unstable device for SYMINDP_LD_M12B_pw
0 0
( 139) unstable device for SYMINDP_LD_M12B_sx
0 0
( 140) unstable device for SYMINDP_LD_m1m
0 0
( 141) unstable device for SYMINDP_LD_m1p
0 0
( 142) unstable device for SYMINDP_LD_bf
0 0
( 143) unstable device for SYMINDP_LD_pw
0 0
( 144) unstable device for SYMINDP_LD_sx
0 0
( 145) unstable device for sub_dev_Device_9240
0 0
( 146) unstable device for CPW1_M1
0 0
( 147) unstable device for CPW2_M1
0 0
( 148) unstable device for CPW1_M1
0 0
( 149) unstable device for CPW2_M2
0 0
( 150) unstable device for CPW1_M3
0 0
( 151) unstable device for CPW2_M3
0 0
( 152) unstable device for CPW1_M4
0 0
( 153) unstable device for CPW2_M4



.......


Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/avnx

Starting //cadence/assura317/tools/assura/bin/nvn //CC10_v6.rsf -
postExtract -exec1 -cdslib //cds.lib
@(#)$CDS: nvn_64 version av3.1roduction:dfII5.1.41-64b:5.10.41-64b.
500.3.31 07/10/2008 02:05 (sfrh121) $
sub-version 317_USR2_HF10, integ signature 2008-07-08-0653
run on...
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
dioDevice("havar" ("PLUS" "MINUS" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("dgdtcap" ("PLUS" "MINUS" nil))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("mimcap" ("HT" "QT" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("mimhk" ("HK" "QK" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("vncap" ("IN" "OUT" "SUB"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("pcap" ("G" "D" "B"))
If this device has more terminals place the parentheses
accordingly.
*WARNING* The terminals are not in parentheses. This is old syntax and
will
be interpreted as a device with fixed terminal number.
The rule will be converted internally to new syntax:
capDevice("ncap" ("G" "D" "B"))

......

function parSubcont redefined
function INDcomp redefined
*WARNING* the rule 'filter' has been converted into 'filterOptions'
with the same function.
*WARNING* bindingFile - 'if(' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'avSwitch(' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'resimulate_extracted' is not a valid keyword
on line 14. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'then' is not a valid keyword on line 14.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 43.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'if(' is not a valid keyword on line 44.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - '!avSwitch(' is not a valid keyword on line
44. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'resimulate_extracted' is not a valid keyword
on line 44. Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - ')' is not a valid keyword on line 44.
Expecting C, N, I, .case, .nocase, CW, NW, or IW
*WARNING* bindingFile - 'then' is not a valid keyword on line 44.
Expecting C, N, I
......

Preprocessing schematic network phase 1
Preprocessing layout network phase 1
*WARNING* resDevice - cell 'silres' not found.
*WARNING* resDevice - cell 'kxres' not found.
*WARNING* resDevice - cell 'oprppres' not found.
*WARNING* resDevice - cell 'opndres' not found.
*WARNING* resDevice - cell 'nwres' not found.
*WARNING* resDevice - cell 'lvsres' not found.
*WARNING* resDevice - cell 'lvspadres' not found.
*WARNING* resDevice - cell 'efuse' not found.
*WARNING* bjtDevice - cell 'vpnp' not found.
*WARNING* mosDevice - cell 'zvtnfet' not found.
*WARNING* mosDevice - cell 'zvtdgnfet' not found.
*WARNING* mosDevice - cell 'pfet_rf' not found.
*WARNING* mosDevice - cell 'nfetarray2' not found.
*WARNING* mosDevice - cell 'nfetarray' not found.
*WARNING* mosDevice - cell 'lvtpfet_rf' not found.
*WARNING* mosDevice - cell 'lvtpfet' not found.
*WARNING* mosDevice - cell 'lvtnfet_rf' not found.
*WARNING* mosDevice - cell 'lvtnfet' not found.
*WARNING* mosDevice - cell 'svtpfet' not found.


........

WARNING* genericDevice("dgxnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgxnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgvnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgvnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("svtnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("svtnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("hvtnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("hvtnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("lvtnfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("lvtnfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("nfettw4_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("nfettw_rf") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgxnfettw4") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgxnfettw") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgvnfettw4") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgvnfettw") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgnfettw4") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("dgnfettw") - cell does not exist. This
command will be ignored.
*WARNING* genericDevice("svtnfettw4") - cell does not exist. This
command will be ignored.

.....

Preprocessing schematic network phase 2
Preprocessing layout network phase 2
*WARNING* pin swapping defined for both schematic and layout.
Using the schematic version.
Schematic Cell:
swapPins("bondpad(Generic)" "(f in gp sub)")
Layout Cell:
swapPins("bondpad(Generic)" "(f in gp sub)")

*WARNING* pin swapping defined for both schematic and layout.
Using the schematic version.
Schematic Cell:
swapPins("esdndsx(Generic)" "(f MINUS PLUS)")
Layout Cell:
swapPins("esdndsx(Generic)" "(f MINUS PLUS)")

*WARNING* pin swapping defined for both schematic and layout.
Using the schematic version.
Schematic Cell:
swapPins("esdvpnp(Generic)" "(f E B C)")
Layout Cell:
swapPins("esdvpnp(Generic)" "(f E B C)")

*WARNING* pin swapping defined for both schematic and layout.
Using the schematic version.
Schematic Cell:
swapPins("nfet_rf(MOS)" "(f D G S B)")
Layout Cell:
swapPins("nfet_rf(MOS)" "(f D G S B)")

.......

Top cell CC10_v6 vs CC10_v6 layout VCO
*WARNING* the filterOptions command filterOptions("ncap(CAP)" "XZ"
ignore( "B" ))
will be processed without ignore part
*WARNING* the filterOptions command filterOptions("dgncap(CAP)" "XZ"
ignore( "B" ))
will be processed without ignore part
*WARNING* the filterOptions command filterOptions("opppcres(RES)" "XZ"
ignore( "B" ))
will be processed without ignore part
*WARNING* the filterOptions command filterOptions("pfet_m0(MOS)" "XZ"
ignore( "B" ))
will be processed without ignore part
*WARNING* the filterOptions command filterOptions("nfet_rf(MOS)" "XZ"
ignore( "B" ))
will be processed without ignore part
*WARNING* the filterOptions command filterOptions("nfet_m0(MOS)" "XZ"
ignore( "B" ))
will be processed without ignore part
parFET1comb Resultant: (nil bentgate 0 w 2e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 3e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 4e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 5e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 6e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 7e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 8e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 9e-05 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.0001 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.00011 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.00012 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.00013 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.00014 l 1e-07)
parFET1comb Resultant: (nil bentgate 0 w 0.00015 l 1e-07)

......

Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/nvn

Starting /Linux/sw/request/cadence/assura317/tools/assura/bin/
vldbToRpa CC10_v6.snn CC10_v6.tre CC10_v6.cel

Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/
vldbToRpa

Starting /Linux/sw/request/cadence/assura317/tools/assura/bin/ercChk /
home/hd00/l/lwang04/RF/CC10_v6.rsf

Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/ercChk

Starting /Linux/sw/request/cadence/assura317/tools/assura/bin/
avcallproc /home/hd00/l/lwang04/RF/CC10_v6.rsf -trp -exec1

Finished /Linux/sw/request/cadence/assura317/tools/assura/bin/
avcallproc


Assura LVS terminated normally.



Run ended: Wed Feb 11 14:30:19 2009

***** Assura terminated normally *****











cop0...@gmail.com wrote:

On Feb 11, 10:08 am, cop0...@gmail.com wrote:
Hi Adam,
I'm no expert but judging from the info. regarding number of device
mismatch, could it be due to the difference in parameter of your n-
transistor fingers?
Have you compared the w & l of the transistor in the schematic with
the one in the layout?
Is the compare function working as expected for rf transistors?

I-FAB

Hi,

I mistook your warnings with something else I previously had (which
was early last year).
My problems were due to either (1) wrong definition in the binding
file or (2) wrong device terminal definitions - and they occured on
fixed devices (I don't think an rf transistor instance would be
created as a fixed pcell).
Now, I'm intrigued by the "Pattern ..." warning (as well as the number
of its occurence). Is the device type supposed to be recognised by
text (you would need to check extraction method of the transistor)?
How about try setting avParameter option for the LVS run: ?
abortOnMissingSchematic to t? It might indicate whether the problem
was during extraction of schematic device.
Is there any other helpful message in Assura's generated files
(i.e. .log or .msg files)?
Usually Assura's generated files reveal more details although sifting
through them can be overwhelming even for the simplest errors.

Sorry for the too generic response.

I-FAB

 

[I-F AB]

Hi,
First of all, I take it your really new to Assura, right?
So I'll try to go as simple & clear as I can.

If you open the binding file, it should have something like:
*******************************************************************
.......
c nhp N
c N(MOS) N
c php P
c INDUCTOR XFMR8RFGSGA
c CAPACITOR(CAP) NVAR(CAP)
........
*******************************************************************

The compare rule files have:
*******************************************************************
avCompareRules(
.......
.......
)
*******************************************************************

While the extract rules have:
*******************************************************************
drcExtractRules(
......
layerDefs(
.......
)
.......
)
*******************************************************************

The extract rules have layer definitions (e.g. metal1, metal2 ) as
well
as generated layers used to do DRC/LVS checking (new_layer = geomAnd
( metal1 metal2 ).
These layers are used to identify devices & connectivity.
They also define how to calculate/extract parameters from a single
device.

The compare rules usually have procedures to tell you how devices are
recognised (e.g. series & parallel resistors merged into 1 resistor).

The bind files would say the equivalence of a device in schematic to a
device in layout.

I believe, you are just not using the right input files for the run.
I think this should be a good start for running Assura. Now, debugging
a mismatch is a different issue and more complex, but what I can say
is the generated files come in very handy, although they can seem
quite puzzling at first.

Hope this helps.
I-FAB

 

[Adam]

I-FAB,

Thanks a lot. Your information is really helpful.

Regards,
Adam

I-F AB wrote:

Hi,
First of all, I take it your really new to Assura, right?
So I'll try to go as simple & clear as I can.

If you open the binding file, it should have something like:
*******************************************************************
......
c nhp N
c N(MOS) N
c php P
c INDUCTOR XFMR8RFGSGA
c CAPACITOR(CAP) NVAR(CAP)
.......
*******************************************************************

The compare rule files have:
*******************************************************************
avCompareRules(
......
......
)
*******************************************************************

While the extract rules have:
*******************************************************************
drcExtractRules(
.....
layerDefs(
......
)
......
)
*******************************************************************

The extract rules have layer definitions (e.g. metal1, metal2 ) as
well
as generated layers used to do DRC/LVS checking (new_layer = geomAnd
( metal1 metal2 ).
These layers are used to identify devices & connectivity.
They also define how to calculate/extract parameters from a single
device.

The compare rules usually have procedures to tell you how devices are
recognised (e.g. series & parallel resistors merged into 1 resistor).

The bind files would say the equivalence of a device in schematic to a
device in layout.

I believe, you are just not using the right input files for the run.
I think this should be a good start for running Assura. Now, debugging
a mismatch is a different issue and more complex, but what I can say
is the generated files come in very handy, although they can seem
quite puzzling at first.

Hope this helps.
I-FAB