Assura LVS Flow with verilog netlist

[dinac]

Hi all,

Using IC 5.14 and Assura 3.16

I want to perform a LVS on verilog synthesized netlist with gds.

Is there a place, where I could get a reference flow to do this on
web? I tried two methods to proceed

1. Van' on verilog netlist and with gds, LVS failed. it said it
could'nt read the gds, so tried the next one.

2.. van on verilog netlist and imported the gds to dfII and tried to
perform the LVS , but the run takes too long and gets hanged.

A little help needed to get through the flow.
Thanks for the help.

cheers
Dinac

 

[S. Badel]

Hi Dinac,

I'm doing this often without any problems, whether the input layout is in GDS or DFII format.

I suggest you use the UI for a start ; later on you can grab the RSF file generated from the UI to
run assura command-line.

You'll have to set the input schematic format to netlist, and include your verilog netlist there (I
suggest using a netlist with explicit power/ground connections, it avoids problems). At this point
you can also include the spice or cdl netlists of your standard cells ; if you do not have them you
will have to define the cells as blackboxes (?blackBoxCell).

For the layout you can use the GDS file directly or import it into virtuoso and select DFII as a source.

It would be useful to see error messages, or to know where exactly your assura run is hanging, to
try and provide some useful input.

Cheers,
Stéphane


dinac wrote:

Hi all,

Using IC 5.14 and Assura 3.16

I want to perform a LVS on verilog synthesized netlist with gds.

Is there a place, where I could get a reference flow to do this on
web? I tried two methods to proceed

1. Van' on verilog netlist and with gds, LVS failed. it said it
could'nt read the gds, so tried the next one.

2.. van on verilog netlist and imported the gds to dfII and tried to
perform the LVS , but the run takes too long and gets hanged.

A little help needed to get through the flow.
Thanks for the help.

cheers
Dinac

 

[dinac]

Hi,

Thanks a lot for your reply Stephane and sorry for the late reply.

Actually now i am facing other problem, the Assura deck might not be
properly implemented.

I have a imported a small digital design with IO and now performing an
LVS with the schematic which is been imported from verilog.

I see in LVS there are mismatches with ptap (gnd! to sub!) devices in
most of the standard cells, and hence also mismatch on the nets that
should be defining it. But LVS runs clean, when I perform on these
standardcells seperatelly from the library.

The layout netlist (.lnn file) did not dump the information of the
ptap or the line defining the ptap was missing for the cells in the
design.

Any clue on this.

Thanks

cheers
Dinac