assignment with *when* statement

[Valentin Tihomirov]

1. Why this works only in architecture body?
A <= 0 when A = 9 else A + 1;
-- and this
with A select
A <= 0 when 9,
<= (A + 1) when others;

But not in clocked process? I have to write
A <= A + 1;
if A = 9 then
A <= 0;
end if;



2. In addition, I cannot force my compiler to analyze this

signal A: std_logic;
signal I: integer;

A <= (I = 10); -- how can I convert bool into std_logic?

I have to write
A <= '1' when (I = 10) else '0';

 

[Shaomin]

Valentin Tihomirov wrote:

1. Why this works only in architecture body?
A <= 0 when A = 9 else A + 1;
-- and this
with A select
A <= 0 when 9,
= (A + 1) when others;
Above is concurrent assignment;

But not in clocked process? I have to write
A <= A + 1;
if A = 9 then
A <= 0;
end if;
Above is sequential assignment;

2. In addition, I cannot force my compiler to analyze this

signal A: std_logic;
signal I: integer;

A <= (I = 10); -- how can I convert bool into std_logic?

I have to write
A <= '1' when (I = 10) else '0';


You could define boolean true and false as 1 and 0

 

[Mike Treseler]

Valentin Tihomirov wrote:

I have to write
A <= '1' when (I = 10) else '0';

signal A: std_logic;
signal I: integer;

function active_high (arg : boolean)
return std_ulogic is begin
if arg then
return '1';
else
return '0';
end if;
end function active_high;

begin

A <= active_high(I = 10);


-- Mike Treseler

 

[Valentin Tihomirov]

Isn't there such a function in a standard library/package?

 

[Valentin Tihomirov]

The assignments in architecture body are concurrent while are sequential in
a clockecd process. I just want to understand why I can use
A <= 0 when SpecialCase else A + 1;
in a concurrent assignment but cannot in a seqential assignment and have to
use if-then-else instead? The combinational logic should be the same, the
only difference is a register at ist output in a sequential assignment.

 

[Jonathan Bromley]

"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in
message news:3FA04B33.6090304@flukenetworks.com...

A <= '1' when (I = 10) else '0';

signal A: std_logic;
signal I: integer;

function active_high (arg : boolean)
return std_ulogic is begin
if arg then
return '1';
else
return '0';
end if;
end function active_high;

begin

A <= active_high(I = 10);

Another formulation, which I find aesthetically pleasing:

type sul_bool is array(boolean) of std_ulogic;
constant active_high: sul_bool := (
FALSE => '0' ,
TRUE => '1' );
signal A: std_logic;
signal I: integer;
begin
A <= active_high(I = 10);

Sadly you can't use a lookup-table "conversion function"
of this kind in a port map.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

"Valentin Tihomirov" <valentin@abelectron.com> wrote in
message news:bnqqj7$153sq3$1@ID-212430.news.uni-berlin.de...

I just want to understand why I can use
A <= 0 when SpecialCase else A + 1;
in a concurrent assignment but cannot in a seqential
assignment and have to use if-then-else instead?

It is a curiosity of the way VHDL syntax was defined.

At base, EVERYTHING in VHDL is a process - so the language
has rules that define how concurrent assignments, concurrent
procedure calls etc. can be rewritten as processes. Here
is the rewriting rule for your conditional signal assignment:

1) Write the equivalent if-then-else procedural statement:

if SpecialCase then
A <= 0;
else
A <= A + 1;
end if;

2) Determine all the signals that take part in calculation
of the right-hand-side of the assignment, and use
them to build a sensitivity-list "wait" statement:

wait on SpecialCase, A;

3) Put those two statements in a process:

process begin
if SpecialCase then
A <= 0;
else
A <= A + 1;
end if;
wait on SpecialCase, A;
end process;

So far, so good. All this is very clear. What is slightly
less clear is why you can't simply use "if" and "case"
statements as concurrent statements, instead of the curious
conditional and selected assignments. But that's the way
it was defined, so we must live with it.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Brian Drummond]

On Thu, 30 Oct 2003 12:52:06 +0200, "Valentin Tihomirov"
<valentin@abelectron.com> wrote:

The assignments in architecture body are concurrent while are sequential in
a clockecd process. I just want to understand why I can use
A <= 0 when SpecialCase else A + 1;
in a concurrent assignment but cannot in a seqential assignment and have to
use if-then-else instead? The combinational logic should be the same, the
only difference is a register at ist output in a sequential assignment.

Probably to distinguish clearly between concurrent and sequential styles

of programming. Let the compiler catch a lot of potential errors, and
make it clear to readers which programming domain you are in.

VHDL has elements of two completely different styles of programming
language. Concurrent assignments are essentially a form of functional
programming (think SASL, Haskell, Miranda) - as an easy and natural way
of expressing parallelism, while within a process you have a (modified)
form of sequential programming, as in C or Pascal. (One obvious
modification is the deferred assignment to signals - if you need
immediate assignment, use variables instead. Again, the two assignment
symbols <= and := help keep the distinction clear)

Think of it as two separate languages in one, trying hard not to step on
each other's toes.

- Brian

 

[Valentin Tihomirov]

I understand which clauses lead to which logic (combinational or
sequential). I wanted to understand why two different clauses are used to
express the same logic? Namely, why if-then-else clause is good for
sequential while select is good for combinational? The statement

A <= 0 when SpecialCase else B + 1;

generates a MUX2 with 2 inputs:
- B + 1;
- 0;

The output of the mux is fed to signal A. Why should I use if-then-else
caluse instead to implement the same MUX when its output is fed to reg A
input?

VHDL has special expression like
if RisingEdage(CLK)
to distinguish between combinational and synchronous logic. Why to enforce
it with if-then redundancy?

 

[Allan Herriman]

On Thu, 30 Oct 2003 11:23:07 -0000, "Jonathan Bromley"
<jonathan.bromley@doulos.com> wrote:

"Valentin Tihomirov" <valentin@abelectron.com> wrote in
message news:bnqqj7$153sq3$1@ID-212430.news.uni-berlin.de...

I just want to understand why I can use
A <= 0 when SpecialCase else A + 1;
in a concurrent assignment but cannot in a seqential
assignment and have to use if-then-else instead?

It is a curiosity of the way VHDL syntax was defined.

s/curiosity/mistake/

IMHO, this feature makes VHDL harder to learn. I imagine it also
makes it harder to parse. I believe it only exists for historical
reasons.

Most users think of a signal assignment as

target <= expression;

or a variable assignment (or constant initialisation) as

target := expression;

Easy so far, until you find out that the syntax of 'expression' varies
depending on where the assignment is taking place. Not good.

So far, so good. All this is very clear. What is slightly
less clear is why you can't simply use "if" and "case"
statements as concurrent statements, instead of the curious
conditional and selected assignments. But that's the way
it was defined, so we must live with it.

I believe the VHDL 200x folk (the Modeling and Productivity group) are
doing something about this.

Hopefully we will be able to do this:

constant foo : integer = 7 when bar else 3;

Using the current language definition, I would need to create a
function to do the job of that simple expression.

Regards,
Allan.

 

[Klaus Falser]

In article <bnqsau$ie$1$830fa795@news.demon.co.uk>, jonathan.bromley@doulos.com says...
....

So far, so good. All this is very clear. What is slightly
less clear is why you can't simply use "if" and "case"
statements as concurrent statements, instead of the curious
conditional and selected assignments. But that's the way
it was defined, so we must live with it.

I'm not so good at the finenesses of the english language, but my
impression was always that
- "if" expresses better that a decision is made once and
- "when" implies that this decision is made all the time

Maybe that's the reason two different terms were used.

Best regards

--
Klaus Falser
Durst Phototechnik AG
kfalser@IHATESPAMdurst.it

 

[Jonathan Bromley]

hi Klaus,
"Klaus Falser" <kfalser@IHATESPAMdurst.it> wrote in message
news:MPG.1a0c3a3c5f15e6af98969b@151.99.250.3...

I'm not so good at the finenesses of the english language, but my
impression was always that
- "if" expresses better that a decision is made once and
- "when" implies that this decision is made all the time

Maybe that's the reason two different terms were used.

Your fine distinctions among prepositions are very good!

However, I have a counter-example:

loop
...
exit when <condition>;
...
end loop;

This use of "when" expresses rather badly the idea that
a decision is made at one point in time - I agree with your
understanding, and I think that "if" would have been a better
choice for this syntax!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Valentin Tihomirov]

I'm not so good at the finenesses of the english language, but my
impression was always that
- "if" expresses better that a decision is made once and
- "when" implies that this decision is made all the time

I don't understand these linguistic details. But in the context of HW/SW
when we check condition in a continous loop the difference IMO is neglable.

in loop1
if <condition> then
B := <value1>;
else
B := <value2>;
end if;
end loop1;

IMO is absolutely equal in common sense with expression

in loop2
B := <value1> when <condition> else <value2>;
end loop2;


The second is just less cumbersome.

 

[Jim Lewis]

Valentin Tihomirov wrote:

I don't understand these linguistic details. But in the context of HW/SW
when we check condition in a continous loop the difference IMO is neglable.

in loop1
if <condition> then
B := <value1>;
else
B := <value2>;
end if;
end loop1;

IMO is absolutely equal in common sense with expression

in loop2
B := <value1> when <condition> else <value2>;
end loop2;


The second is just less cumbersome.

I agree. And it is currently FT10 in the VHDL-200X fast
track proposal list. See:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html

Based on some of the thoughts out there, do you think that
the following would be better syntax (if we allow it
everywhere)?

B := <value1> if <condition> else <value2>;


Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[fe]

Based on some of the thoughts out there, do you think that
the following would be better syntax (if we allow it
everywhere)?

B := <value1> if <condition> else <value2>;

No. just add the when-else everywhere (probably easier to parse).

If you want to change absolutely the inline conditional statement syntaxe,
use something more compact like :

B := <condition> ? <true value> : <false value> ; (C / verilog syntaxe)

B := <true value> ? <condition> : <false value> ; (vhdl when-else style but
doesn't need space)

B := ?(<condition> , <true value> , <false value&gt ; (vhdl function style)
....

regards
fe

 

[VhdlCohen]

No. just add the when-else everywhere (probably easier to parse).

If you want to change absolutely the inline conditional statement syntaxe,
use something more compact like :

B := <condition> ? <true value> : <false value> ; (C / verilog syntaxe)

B := <true value> ? <condition> : <false value> ; (vhdl when-else style but
doesn't need space)

B := ?(<condition> , <true value> , <false value&gt ; (vhdl function style)
...

This will never be approved because it violates the basic rule of VHDL:
Readability.
You could argue that the
condition> ? <true value> : <false value> or the
<true value> ? <condition> : <false value>
syntax is "readable", but I would argue that it is more criptic.
In fact, when I don't use Verilog for a long time, I always find myself
referring the
syntax (I use Sutherland notes
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html)
Ben Cohen
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[fe]

This will never be approved because it violates the basic rule of VHDL:
Readability.
You could argue that the
condition> ? <true value> : <false value> or the
true value> ? <condition> : <false value
syntax is "readable", but I would argue that it is more criptic.

Your argument is a little bit weak, but anyway it's not important.

I think this syntax (?: or if-else) should never be approved because we
don't want to change the existing vhdl syntax (or add new syntax to do the
same thing) but add new functionnality/flexibility.

We must keep anyway the when-else in the concurrent part for backward
compatibility. So just permit usage of the inline condionnal statement
(when-else) everywhere to simplify the number of keyword/syntax to parse.
see bellow for other comments.

In fact, when I don't use Verilog for a long time, I always find myself
referring the
syntax (I use Sutherland notes
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html)

Any language that you didn't use for a long time, vhdl included, you need a
syntax reference.

For vhdl 200x we could permit everywhere too:
if then-elsif then-else-end if
case-when-end case
for loop-end loop

An if <condition> then with a constant condition is equivalent to if
<condition> generate. So by permitting the use of if then-elsif
then-else-end if everywhere, we don't need to create an elsif generate and
else generate.

Same thing for case, no need for a case generate

for loop can replace the for generate just to simplify the language for the
new users (only one syntax to remember).

Inside a process and outside a process, we should use the same syntax to do
the same (equivalent) thing. Keep it simple. For a parser (syntax checking)
it's easier. VHDL is the best HDL, it's just a question of tweaking it.

Example:
when-else in architecture declarative section
(inline structure it's often harder to read because lines become long and
they must be cut)

architecture .... of .... is
constant C_ABC : integer := G_WIDTH when G_XYZ else
G_WIDTH+1 when G_MNO else
G_WIDTH-1;

could be also written with
if then-elsif then-else-end if in architecture declarative section
(it's often easier to read someting without an inline structure because
lines are shorter)

architecture .... of .... is
if G_XYZ then
constant C_ABC : integer := G_WIDTH;
elsif G_MNO then
constant C_ABC : integer := G_WIDTH+1;
else
constant C_ABC : integer := G_WIDTH-1;
end if;


if then-elsif then-else-end if in architecture concurrent section
(equivalent to if generate)

if G_XYZ then
u1: entity work.abc
generic map(
)
port map (
);
else
u2: entity work.def
generic map(
)
port map (
);
end if;


I see that some people work on a wilcard for the sensitivity list. Please
don't add a new keyword ('all' like the proposition), use the known wildcard
'*' like in unix, dos/windows, verilog, ...
process (*)
process (all) could be non backward compatible (you have more chance to be
hit by a ligthning but just in case).

with you proposition in vhdl200x, this process will have a different
behaviour in simulation.
process (all) -- vhdl 93 (simulation only, not for synthesis)
begin
if all then
abc <= xyz;
else
abc <= def;
end if;
end process;


What do you (Jim, Ben, anybody) think about these?

regards
fe