assignment question

[Sen-Lung Chen]

Dear All:
I have a question about Verilog.I write a code as below.But it fails
in compile.

reg [4:0]Conf_reg;
reg [1:0]Mux_reg;

always@(Conf_reg)
begin
casex(Conf_reg)
5'bxxxx1: Mux_reg = 2'b11;
5'bxxx10: Mux_reg = 2'b10;
5'bxx100: Mux_reg = 2'b01;
default : Mux_reg = 2'b00;
endcase
end
endmodule

the error message is
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
"re_LFSR.v", 87: Mux_reg = 2'b11;

How should I fix it?..
Thanks a lot for your help.

 

[Sen-Lung Chen]

I found the question. Thanks a lot.
I have another question:
I define a module

module
controller(Conf_reg,Mem_reg,Char_reg,Out_reg,Mux_reg,Final_LFSR);
input [4:0]Conf_reg;
input [4:0]Mem_reg;
input [2:0]Char_reg;
output [4:0]Out_reg;
output [1:0]Mux_reg;
output [3:0]Final_LFSR;

......

Now. I use the module

reg [2:0]char_reg;
reg [4:0]Conf_temp;
reg [2:0]Mem_temp;
reg [4:0]Mem;
reg [1:0]mux_sel;
reg [3:0]LFSR_temp;

controller c1(Conf_temp,Mem_temp,char_reg,Mem,mux_sel,LFSR_temp);

The error message is
Error! Illegal output port specification (port 3)
[Verilog-IOPSP]
"re_LFSR.v", 131: Mem


Error! Illegal output port specification (port 4)
[Verilog-IOPSP]
"re_LFSR.v", 131: mux_sel


Error! Illegal output port specification (port 5)
[Verilog-IOPSP]
"re_LFSR.v", 131: LFSR_temp

Thanks for your help.

 

[Sen-Lung Chen]

I found the question. Thanks a lot.
I have another question:
I define a module

module
controller(Conf_reg,Mem_reg,Char_reg,Out_reg,Mux_reg,Final_LFSR);
input [4:0]Conf_reg;
input [4:0]Mem_reg;
input [2:0]Char_reg;
output [4:0]Out_reg;
output [1:0]Mux_reg;
output [3:0]Final_LFSR;

......

Now. I use the module

reg [2:0]char_reg;
reg [4:0]Conf_temp;
reg [2:0]Mem_temp;
reg [4:0]Mem;
reg [1:0]mux_sel;
reg [3:0]LFSR_temp;

controller c1(Conf_temp,Mem_temp,char_reg,Mem,mux_sel,LFSR_temp);

The error message is
Error! Illegal output port specification (port 3)
[Verilog-IOPSP]
"re_LFSR.v", 131: Mem


Error! Illegal output port specification (port 4)
[Verilog-IOPSP]
"re_LFSR.v", 131: mux_sel


Error! Illegal output port specification (port 5)
[Verilog-IOPSP]
"re_LFSR.v", 131: LFSR_temp

Thanks for your help.

 

[John_H]

First, please do yourself a favor and use named ports whenever
reasonable. There are times when ordered port lists are the preferred
way to go because the fully named list would take up so much space.

As for your issue: Please note that the outputs from a module should go
to "wire" elements, not "reg" elements.

I'd suggest using the module in the following form with the three
outputs declared as wires and the named port list for clarity:

reg [2:0] char_reg;
reg [4:0] Conf_temp;
reg [2:0] Mem_temp;
wire [4:0] Mem;
wire [1:0] mux_sel;
wire [3:0] LFSR_temp;

controller c1
( .Conf_reg ( Conf_temp )
, .Mem_reg ( Mem_temp )
, .Char_reg ( char_reg )
, .Out_reg ( Mem )
, .Mux_reg ( mux_sel )
, .Final_LFSR ( LFSR_temp )
);



Sen-Lung Chen wrote:

I found the question. Thanks a lot.
I have another question:
I define a module

module
controller(Conf_reg,Mem_reg,Char_reg,Out_reg,Mux_reg,Final_LFSR);
input [4:0]Conf_reg;
input [4:0]Mem_reg;
input [2:0]Char_reg;
output [4:0]Out_reg;
output [1:0]Mux_reg;
output [3:0]Final_LFSR;

.....

Now. I use the module

reg [2:0]char_reg;
reg [4:0]Conf_temp;
reg [2:0]Mem_temp;
reg [4:0]Mem;
reg [1:0]mux_sel;
reg [3:0]LFSR_temp;

controller c1(Conf_temp,Mem_temp,char_reg,Mem,mux_sel,LFSR_temp);

The error message is
Error! Illegal output port specification (port 3)
[Verilog-IOPSP]
"re_LFSR.v", 131: Mem


Error! Illegal output port specification (port 4)
[Verilog-IOPSP]
"re_LFSR.v", 131: mux_sel


Error! Illegal output port specification (port 5)
[Verilog-IOPSP]
"re_LFSR.v", 131: LFSR_temp

Thanks for your help.