Assignment of vectors of non-matching lengths

[zigi]

Hi All

I've received some Verilog code that I'm trying to figure out. In the
code there is an assignment from a long vector into a short vector:

reg [81:0] long_reg;
reg [25:0] short_reg;

....
....
....
short_reg <= long_reg;

I know that if I would write that in VHDL the synthisizer would not
let it slide. How does Verilog treat this? Is there a standard way?
How would Xilinx's XST treat this?

Thanks

Zigi

 

[Muzaffer Kal]

On Thu, 5 Mar 2009 15:36:54 -0800 (PST), zigi <drabkins@gmail.com>
wrote:

Hi All

I've received some Verilog code that I'm trying to figure out. In the
code there is an assignment from a long vector into a short vector:

reg [81:0] long_reg;
reg [25:0] short_reg;

...
...
...
short_reg <= long_reg;

I know that if I would write that in VHDL the synthisizer would not
let it slide. How does Verilog treat this? Is there a standard way?

In Verilog, the right hand side is truncated if it's longer than left
hand side so your assignment would be identical to:

short_reg <= long_reg[25:0];

In general this can change the sign of the result if the RHS
expression is signed.

Also the RHS of an assignment is extended (zero or sign if RHS is
signed) if its length is shorter.

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

 

[Jonathan Bromley]

On Thu, 05 Mar 2009 15:45:38 -0800, Muzaffer Kal wrote:

In Verilog, the right hand side is truncated if it's longer than left
hand side

Yes.

Also the RHS of an assignment is extended (zero or sign
if RHS is signed) if its length is shorter.

This also is true, but beware: it is by no means obvious
what "RHS is signed" means. The rules are complicated.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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