Assignment and logical test

[Kenneth Brun Nielsen]

Can I do both an assignment and a logical check in once?

E.g. I want to do something similar to:

r = $fgets(textline,fd);
if ((checkNum = $sscanf(textline," %1b %1b\n",inputBit1,inputBit2)) >
0)
$display("Input stimuli read (%d)",checkNum);
else if((checkNum = $sscanf(textline,"* %s \n",comment)) > 0)
$display("Comment read: %s",comment);
else
$display("Input line format not recognized: %s", comment);

The "if" line is the problem. Something similar to the above would be
simpler than (particularly for many else-if cases):
checkNum =$sscanf(textline," %1b %1b\n",inputBit1,inputBit2);
if (checkNum > 0)
$display("Input stimuli read (%d)",checkNum);
else
begin
checkNum = $sscanf(textline,"* %s \n",comment);
if (checkNum > 0)
$display("Comment read: %s",comment);
else
begin
...
end
end

Best regards,
Kenneth

 

[Jonathan Bromley]

On Thu, 30 Jul 2009 05:49:36 -0700 (PDT), Kenneth Brun Nielsen wrote:

Can I do both an assignment and a logical check in once?

Not in regular Verilog.

SystemVerilog permits it, with the proviso that
you must add an extra pair of parentheses to
convince the compiler that you really meant it:

if ( a = some_function(b) )

is illegal; the compiler thinks you probably
meant "==" and chokes. But this is OK:

if ( (a = some_function(b)) )

because you're now forcing the assignment to
look like an expression by enclosing it in ().

I'm not sure how many simulators have already
implemented this. Caveat scriptor.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.