Assigning arrays of different types

[ALuPin@web.de]

Hi,

I am trying the following:


library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture rtl of test is

subtype stype_2b is std_logic_vector(1 downto 0);
type type_ch_array is array (natural range <&gt of stype_2b;
type type_ch is array (natural range <&gt of stype_2b;


signal ls_array : type_ch_array(15 downto 0);

signal ls_subarray : type_ch(3 downto 0);

begin

ls_array(3 downto 0) <= ls_subarray;

end rtl;

Can someone explain why the compiler complains about
that assignment ?

Rgds

 

[Alan Fitch]

ALuPin@web.de wrote:

Hi,

I am trying the following:


library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture rtl of test is

subtype stype_2b is std_logic_vector(1 downto 0);
type type_ch_array is array (natural range <&gt of stype_2b;
type type_ch is array (natural range <&gt of stype_2b;


signal ls_array : type_ch_array(15 downto 0);

signal ls_subarray : type_ch(3 downto 0);

begin

ls_array(3 downto 0) <= ls_subarray;

end rtl;

Can someone explain why the compiler complains about
that assignment ?

Rgds

Yes, because you are trying to assign objects of two different types to
each other, ahd VHDL is a strongly typed language.

ls_array is of type type_chr_array
ls_subarray is of type type_ch

However they are "closely related types" because they are both arrays
with the same number of dimensions, the same element types, and the same
index type.

So

ls_array(3 downto 0) <= type_ch_array(ls_subarray);

should work.

The situation is exactly analogous to signed/unsigned/std_logic_vector.

regards
Alan

P.S. If you really want to blow your mind try declaring a new integer
type



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Alan Fitch
Senior Consultant

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[ALuPin@web.de]

Thank you, the explanation is very clear.

Best regards