"assign" warnings after synthesis

[Verictor]

Hi,

I obtained some "assign" warnings after synthesis. I understand why
but how do I remove them? Here is a simple example of my circuit:

output a;
wire a_wire;

always @(posedge clk) begin
call_module(.something(a_wire), ...); // call_module is another
module
....
end

assign a = a_wire;

In this case, since a and a_wire are the same, synthesis tool just
optimized it and issued an "assign" warning. If looking into the
netlist, we will see this

assign a = nxxx;

How do I solve this?

Thanks.