Assign statements in my synthesized circuit?

Is it normal to have assign statements in a synthesized circuit?

My understanding was that a properly synthesized circuit shud only
contain gates.

Is there degrees of synthesized-ness? Fully/partial etc where some have
assigns and some not?

Does the presence of assign statements distinguish between a gate level
netlist and a synthesized circuit?

Any help wud be appreciated.


Rob


:-S

 

[mk]

On 30 Aug 2006 05:19:38 -0700, robquigley@gmail.com wrote:

Is it normal to have assign statements in a synthesized circuit?

My understanding was that a properly synthesized circuit shud only
contain gates.

Is there degrees of synthesized-ness? Fully/partial etc where some have
assigns and some not?

Does the presence of assign statements distinguish between a gate level
netlist and a synthesized circuit?

Any help wud be appreciated.

Assign statements in gate level output are usually the result of
missing buffers and mostly result from two output ports driven by the
same pin. Almost all synthesis tools have an option to replace the
assigns with pre-selected buffers. P&R tools usually don't like assign
statement but some of them can do the buffer replacement themselves.
HTH.

 

[gongguowang@yahoo.com]

you shoud add 2 statements below before "compile"
set verilogout_no_tri true

set_fix_multiple_port_nets -all -buffer_constants


mk 写道：

On 30 Aug 2006 05:19:38 -0700, robquigley@gmail.com wrote:

Is it normal to have assign statements in a synthesized circuit?

My understanding was that a properly synthesized circuit shud only
contain gates.

Is there degrees of synthesized-ness? Fully/partial etc where some have
assigns and some not?

Does the presence of assign statements distinguish between a gate level
netlist and a synthesized circuit?

Any help wud be appreciated.

Assign statements in gate level output are usually the result of
missing buffers and mostly result from two output ports driven by the
same pin. Almost all synthesis tools have an option to replace the
assigns with pre-selected buffers. P&R tools usually don't like assign
statement but some of them can do the buffer replacement themselves.
HTH.

 

[mk]

On 4 Sep 2006 03:20:54 -0700, "gongguowang@yahoo.com"
<gongguowang@yahoo.com> wrote:

you shoud add 2 statements below before "compile"

set verilogout_no_tri true
set_fix_multiple_port_nets -all -buffer_constants

This is for DC from Synopsys; what about Cadenc (RC) and Magma
(BlastCreate) ?