assign statement in netlist

[rajan]

Hi,

I would like to know that how to generate a synthesized netlist that doesn't
contain ASSIGN statement (in synthesized netlist).

Wait for your response.

rajan

 

[Kholdoun TORKI]

Hi Rajan,

This is a durty way to solve the problem, and it may be
dangerous in some situations, especially if you use a small
buffer.
Of course the timing may be affected, and the functionnality
may also be affected.

Why are you trying to solve this "assign" statement ?
Most of the modern backend tools (Silicon Ensemble
or SOC Encounter ...) accept those statement, and process
them correctly.
Annotated and backannotated simulations accept also
those statements.

Have you tried the setup variables and commands below ?
The only situation where you may still have "assign"
statements in that case, will be when you have
instance blocks with "don't touch" instruction.

Regards,
=================
Kholdoun TORKI
http://cmp.imag.fr
==================


rajan wrote:

Hi,

So, does it give problem if we insert buffers manually (for these assign
statements).
I feel that the timing in the netlist might be affected.

Thank you.


"Kholdoun TORKI" <Kholdoun.Torki@imag.fr> wrote in message
news:cgn24p$9a3$1@trompette.imag.fr...

In addition to the Alexander suggestion, there is also one
other variable to setup in your ".synopsys_dc_setup" :

verilogout_no_tri = "true"
write_name_nets_same_as_ports = "true"

And also a command to be setup just before the optimization
step :

set_fix_multiple_port_nets -all

Unfortunately this last command cannot be set as a global
variable, you have to activate it on the module you are
optimizing and this should be done just before launching
the optimization.

Long time ago Synopsys have had a better way to do this by a
global variable, but this is not the case for the recent
versions of Design Compiler.

On the other hand, I would recommand you to execute the
"change_names" command before writting your Verilog or VHDL
netlist, respectively by the 2 commands below :

change_names -rules verilog -hierarchy -verbose > change_names.v
change_names -rules vhdl -hierarchy -verbose > change_names.vhd

Hope this helps.

Regards,
=================
Kholdoun TORKI
http://cmp.imag.fr
==================



Alexander Gnusin wrote:


"rajan" <rajan100000@hotmail.com> wrote in message

news:<cglbmn$ebp$1@reader08.wxs.nl>...

Hi,

I would like to know that how to generate a synthesized netlist that

doesn't

contain ASSIGN statement (in synthesized netlist).

Wait for your response.

rajan


There are 2 reasons why DC uses ASSIGN:

1. Input port connected directly to output port
2. Tristate cells such as IO buffers

For the first one, there is only one solution: correct the netlist
inserting the buffer between ports.
For the second one, set variable verilogout_no_tri to true (set
verilogout_no_tri true) before writing the netlist.

Regards,
Alexander Gnusin