assign statement behaviour in diff simulators

[adarsh arora]

I have used NCSim,modelsim,vcs simulators for running the following
continous assign statements:
assign #(rise,fall) b = a;
i found very different beh. in vcs simulator(by Synopsys) from
modelsim and ncsim(Verilog-XL) behaviour.
What should be actual beh. of the above statement.
Shall the new value(event) of a should override its previous scheduled
assignment or something else.

 

[Steven Sharp]

adarsh_arora@hotmail.com (adarsh arora) wrote in message news:<b2a3f8e.0310190942.53f92fb6@posting.google.com>...

I have used NCSim,modelsim,vcs simulators for running the following
continous assign statements:
assign #(rise,fall) b = a;
i found very different beh. in vcs simulator(by Synopsys) from
modelsim and ncsim(Verilog-XL) behaviour.
What should be actual beh. of the above statement.
Shall the new value(event) of a should override its previous scheduled
assignment or something else.

In general, it should override its previous scheduled value. We would
need to see a specific example of delay values, and input change times
to comment on the exact behavior.

If you want an "official" description, the IEEE standard says:

"In situations where a right-hand side operand changes before a previous
change has had time to propagate to the left-hand side, then the following
steps are taken:

a) The value of the right-hand side expression is evaluated.

b) If this RHS value differs from the value currently scheduled to
propagate to the left-hand side, then the currently scheduled
propagation event is descheduled.

c) If the new RHS value equals the current left-hand side value, no
event is scheduled.

d) If the new RHS value differs from the current LHS value, a delay is
calculated in the standard way, using the current value of the left-hand
side, and the delays indicated on the statement; a new propagation event
is then scheduled to occur delay time units in the future."