Assign construct and Memories

[pallav]

I'm trying to get reacquainted with Verilog (after 3-4 years). I'm
building a model of a simple memory module. The partial code is as
follows:

module dram #(parameter DRAMSIZE = 8192, parameter ADRWIDTH = 13)
(input ph1, ph2, // non-overlapping phase
clocks
input reset, // synchronous reset
input [ADRWIDTH-1:0] addr, // address
input [3:0] byteen, // byte enable mask
input rwb, en, // read/write bar, memory
enable
inout [31:0] data, // bi-directional data
output done); // memory operation
complete

reg [31:0] DRAM[DRAMSIZE-1:0];
wire [7:0] bytes3, bytes2, bytes1, bytes0;


// assign bytes to data to write to memory depending upon byte
enable mask
assign bytes0 = byteen[0] ? data[7:0] : DRAM[adr][7:0];
assign bytes1 = byteen[1] ? data[15:8] : DRAM[adr][15:8];
assign bytes2 = byteen[2] ? data[23:16] : DRAM[adr][23:16];
assign bytes3 = byteen[3] ? data[31:24] : DRAM[adr][31:24];

....
endmodule // dram

I'm compiling this code using Icarius Verilog and am getting errors on
the assign bytes* statements. The errors are like this:
dram.v:37: parse error
dram.v:37: error: syntax error in continuous assignment
dram.v:38: parse error
dram.v:38: error: syntax error in continuous assignment
dram.v:39: parse error
dram.v:39: error: syntax error in continuous assignment
dram.v:40: parse error
dram.v:40: error: syntax error in continuous assignment


The assign statements look OK to me but I'm not sure if I'm access the
memory correctly. I'm not sure what is the correct syntax for access
particular bits in a given array of regs.

Any ideas what I'm doing wrong? Thanks.

 

[pallav]

Actually, there is a slight syntax error. adr should be addr. So it
should be:

assign bytes0 = byteen[0] ? data[7:0] : DRAM[addr][7:0];
assign bytes1 = byteen[1] ? data[15:8] : DRAM[addr][15:8];
assign bytes2 = byteen[2] ? data[23:16] : DRAM[addr][23:16];
assign bytes3 = byteen[3] ? data[31:24] : DRAM[addr][31:24];

But even with that fix, the same errors exist. Thanks

 

[Glen Herrmannsfeldt]

wrote:
(snip)

;
assign bytes1 = byteen[1] ? data[15:8] : DRAM[adr][15:8];
assign bytes2 = byteen[2] ? data[23:16] : DRAM[adr][23:16];
assign bytes3 = byteen[3] ? data[31:24] : DRAM[adr][31:24];

Yes, I believe that you have to do the indexing and
bit selection separately. That is, separate assign
statements.

(Unless this was changed in a later version of verilog.)

-- glen

 

On Feb 16, 10:27 pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:

  wrote:

(snip)

   assign bytes0 = byteen[0] ? data[7:0] : DRAM[adr][7:0];
   assign bytes1 = byteen[1] ? data[15:8] : DRAM[adr][15:8];
   assign bytes2 = byteen[2] ? data[23:16] : DRAM[adr][23:16];
   assign bytes3 = byteen[3] ? data[31:24] : DRAM[adr][31:24];

Yes, I believe that you have to do the indexing and
bit selection separately.  That is, separate assign
statements.

(Unless this was changed in a later version of verilog.)

-- glen

I believe Glen is correct - you can't do the bit select and word
select in one step.
Use an intermediate wire to get the word value, then select bits out
of that.

wire [31:0] dram_data = DRAM[addr];
assign bytes0 = byteen[0] ? data[7:0] : dram_data[7:0];

John Providenza

 

[pallav]

On Feb 17, 11:21 am, jprovide...@yahoo.com wrote:

On Feb 16, 10:27 pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu


Yes, I believe that you have to do the indexing and
bit selection separately.  That is, separate assign
statements.

(Unless this was changed in a later version of verilog.)

-- glen

I believe Glen is correct - you can't do the bit select and word
select in one step.
Use an intermediate wire to get the word value, then select bits out
of that.

wire [31:0] dram_data = DRAM[addr];
assign bytes0 = byteen[0] ? data[7:0] : dram_data[7:0];

John Providenza

Thanks a lot folks for the help. I will separate
the word/bit selection and see if that works.

 

On Feb 17, 1:27 am, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Yes, I believe that you have to do the indexing and
bit selection separately.  That is, separate assign
statements.

(Unless this was changed in a later version of verilog.)

Verilog-2001 allows it.

 

[Glen Herrmannsfeldt]

sharp@cadence.com wrote:

On Feb 17, 1:27 am, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Yes, I believe that you have to do the indexing and
bit selection separately. That is, separate assign
statements.

(Unless this was changed in a later version of verilog.)

Verilog-2001 allows it.

I still have my two original verilog books from before 2001,
and I was reading about that one not so long ago.

-- glen