Assign clock ou

[fpgaasicdesigner]

Hi all,

How can I synthesize this:
assign clock_out = clock_in; ?

I would like my block to output on a pin the input clock?
But when I synthesize this line stays assign clock_out = clock_in and
will be an issue for the P&R tool.

Thanks

 

[Muzaffer Kal]

On Wed, 24 Mar 2010 09:18:12 -0700 (PDT), fpgaasicdesigner
<fpgaasicdesigner@gmail.com> wrote:

Hi all,

How can I synthesize this:
assign clock_out = clock_in; ?

I would like my block to output on a pin the input clock?
But when I synthesize this line stays assign clock_out = clock_in and
will be an issue for the P&R tool.

In all ASIC synthesis tools, there is a command to replace assign
statements with buffers; you should read your tools documentation to
find it and run it during synthesis.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[fpgaasicdesigner]

On Mar 24, 12:27 pm, Muzaffer Kal <k...@dspia.com> wrote:

On Wed, 24 Mar 2010 09:18:12 -0700 (PDT), fpgaasicdesigner

fpgaasicdesig...@gmail.com> wrote:
Hi all,

How can I synthesize this:
assign clock_out = clock_in; ?

I would like my block to output on a pin the input clock?
But when I synthesize this line stays assign clock_out = clock_in and
will be an issue for the P&R tool.

In all ASIC synthesis tools, there is a command to replace assign
statements with buffers; you should read your tools documentation to
find it and run it during synthesis.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Yes I know this command: setDoAssign -buffer (buffer_name_cell)

But I wondering if it's a common way in RTL Verilog to do this assign
clock_out = clock_in
To be honest I don't know how to do in other manner...

Thanks

 

[fpgaasicdesigner]

On Mar 24, 12:27 pm, Muzaffer Kal <k...@dspia.com> wrote:

On Wed, 24 Mar 2010 09:18:12 -0700 (PDT), fpgaasicdesigner

fpgaasicdesig...@gmail.com> wrote:
Hi all,

How can I synthesize this:
assign clock_out = clock_in; ?

I would like my block to output on a pin the input clock?
But when I synthesize this line stays assign clock_out = clock_in and
will be an issue for the P&R tool.

In all ASIC synthesis tools, there is a command to replace assign
statements with buffers; you should read your tools documentation to
find it and run it during synthesis.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

I know the command for Encounter is: setDoAssign -buffer
{buffer_cell_name}

I was wondering if there was another way to code t in RTL module...

Thanks

 

[John_H]

On Mar 24, 2:15 pm, fpgaasicdesigner <fpgaasicdesig...@gmail.com>
wrote:

I know the command for Encounter is: setDoAssign -buffer
{buffer_cell_name}

I was wondering if there was another way to code t in RTL module...

Thanks

You could always use an explicit buffer primitive instead.

 

[Muzaffer Kal]

On Wed, 24 Mar 2010 11:12:07 -0700 (PDT), fpgaasicdesigner
<fpgaasicdesigner@gmail.com> wrote:

On Mar 24, 12:27 pm, Muzaffer Kal <k...@dspia.com> wrote:
On Wed, 24 Mar 2010 09:18:12 -0700 (PDT), fpgaasicdesigner

fpgaasicdesig...@gmail.com> wrote:
Hi all,

How can I synthesize this:
assign clock_out = clock_in; ?

I would like my block to output on a pin the input clock?
But when I synthesize this line stays assign clock_out = clock_in and
will be an issue for the P&R tool.

In all ASIC synthesis tools, there is a command to replace assign
statements with buffers; you should read your tools documentation to
find it and run it during synthesis.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Yes I know this command: setDoAssign -buffer (buffer_name_cell)

But I wondering if it's a common way in RTL Verilog to do this assign
clock_out = clock_in

You can either use a Verilog buffer primitive
buf ckbuf(clock_out, clock_in);
or instantiate a buffer from your cell library:
BUFX1 ckbuf(.Y(clock_out), .A(clock_in));
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com