assertions

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hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
 
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patlola.santhosh@gmail.com wrote:

iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
Click to expand...
Consider learning how to run a standard
testbench with your simulator before
taking on OVL assertions.

-- Mike Treseler

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Post a sample code and the exact error - your post is so unclear to me,
sorry.

Regards
Ajeetha, CVC
www.noveldv.com
Books:
--------
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, http://www.abv-sva.org
* Using PSL/Sugar

patlola.santhosh@gmail.com wrote:
hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
Click to expand...
 
Ajeetha wrote:
Post a sample code and the exact error - your post is so unclear to me,
sorry.

Regards
Ajeetha, CVC
www.noveldv.com
Books:
--------
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, http://www.abv-sva.org
* Using PSL/Sugar

patlola.santhosh@gmail.com wrote:
hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
iam learning verilog OVL assertions .plese send to me any material
Click to expand...
 
Ajeetha wrote:
Post a sample code and the exact error - your post is so unclear to me,
sorry.

Regards
Ajeetha, CVC
www.noveldv.com
Books:
--------
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, http://www.abv-sva.org
* Using PSL/Sugar

patlola.santhosh@gmail.com wrote:
hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
Click to expand...
 
Ajeetha wrote:
Post a sample code and the exact error - your post is so unclear to me,
sorry.

Regards
Ajeetha, CVC
www.noveldv.com
Books:
--------
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, http://www.abv-sva.org
* Using PSL/Sugar

patlola.santhosh@gmail.com wrote:
hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.
Click to expand...


thise i s my code .please slove me problem.
plese send in materials verilog OVL assertions.
advacecd thanks

/*--------------------- Includes and Defines
-------------------------*/
`define OVL_ASSERT_ON
`define OVL_INIT_MSG
`include "assert_always_on_edge.vlib"
/*---------------------- Module Definition
----------------------------*/
module ctr_4_bit (q, clk, clear);
output [3:0] q;
input clk, clear;
reg [3:0] q;
always @ (posedge clear or posedge clk)
begin
if (clear)
q <= 4'd0;
else q <= q + 1;
end
endmodule
/*----------------------- Stimulus Block
-------------------------------*/
module top;
reg clk, reset;
wire [3:0] q;
ctr_4_bit st (q, clk, reset);
initial
clk = 1'b0;
always #1 clk = ~clk; //toggle clk every 1 time unit
initial
begin
reset = 1'b1; //reset high initially - see waveforms
#1 reset = 1'b0; //reset goes low after 1 nsec
#20 reset = 1'b1; //reset goes high again 20 nsecs later
#1 $finish; //end simulation after these many nsecs.
end
/*---------------------- SHM Dump Block --------------------------*/
initial
begin
$shm_open
("/vdump/santosh/tb_assert_always_on_edge_example.shm");
$shm_probe ("as");
end
/*---------------------- Assertion Block ----------------------------*/
assert_always_on_edge #(
`OVL_ERROR,
`OVL_NEGEDGE, //Transition specified here.
Check if sampling event goes
// from 1 to 0(NOTE: This is transition of an
EVENT, not of a particular line)
`OVL_ASSERT,
"Error: q[2] == 1 at rising clk",
`OVL_COVER_ALL)


check (
clk == 1, //clk

reset == 0, //reset
q[1] == 1, //sampling
event - referenced only once
q[2] == 0); //expr to be checked -
checked only once. throw error if this expr is FALSE
endmodule

/*-------------------------- End
--------------------------------------*/
 
See the code below:

assert_always_on_edge ..... check (clk, ~reset, q[1], q[2]==0);

Regards,
-Alex



santhosh wrote:
Ajeetha wrote:
Post a sample code and the exact error - your post is so unclear to me,
sorry.

Regards
Ajeetha, CVC
www.noveldv.com
Books:
--------
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
http://www.systemverilog.us/
* SystemVerilog Assertions Handbook, http://www.abv-sva.org
* Using PSL/Sugar

patlola.santhosh@gmail.com wrote:
hi All,
iam learnig to assertion OVL using i get some problem in sim vision i
declear in codition in assertions i get error after one cycle .this
error is right or not slove me my problem.



thise i s my code .please slove me problem.
plese send in materials verilog OVL assertions.
advacecd thanks

/*--------------------- Includes and Defines
-------------------------*/
`define OVL_ASSERT_ON
`define OVL_INIT_MSG
`include "assert_always_on_edge.vlib"
/*---------------------- Module Definition
----------------------------*/
module ctr_4_bit (q, clk, clear);
output [3:0] q;
input clk, clear;
reg [3:0] q;
always @ (posedge clear or posedge clk)
begin
if (clear)
q <= 4'd0;
else q <= q + 1;
end
endmodule
/*----------------------- Stimulus Block
-------------------------------*/
module top;
reg clk, reset;
wire [3:0] q;
ctr_4_bit st (q, clk, reset);
initial
clk = 1'b0;
always #1 clk = ~clk; //toggle clk every 1 time unit
initial
begin
reset = 1'b1; //reset high initially - see waveforms
#1 reset = 1'b0; //reset goes low after 1 nsec
#20 reset = 1'b1; //reset goes high again 20 nsecs later
#1 $finish; //end simulation after these many nsecs.
end
/*---------------------- SHM Dump Block --------------------------*/
initial
begin
$shm_open
("/vdump/santosh/tb_assert_always_on_edge_example.shm");
$shm_probe ("as");
end
/*---------------------- Assertion Block ----------------------------*/
assert_always_on_edge #(
`OVL_ERROR,
`OVL_NEGEDGE, //Transition specified here.
Check if sampling event goes
// from 1 to 0(NOTE: This is transition of an
EVENT, not of a particular line)
`OVL_ASSERT,
"Error: q[2] == 1 at rising clk",
`OVL_COVER_ALL)


check (
clk == 1, //clk

reset == 0, //reset
q[1] == 1, //sampling
event - referenced only once
q[2] == 0); //expr to be checked -
checked only once. throw error if this expr is FALSE
endmodule

/*-------------------------- End
--------------------------------------*/
Click to expand...
 
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