Assertion file update problem in ModeSim (via Tcl script)

[Alex]

Hi guys,

I experience some problem with modeling some designs in ModelSim 5.7 XE
2/Starter trough Tcl script.

I have a set of designs with corresponding testbenches, and while running
simulations through

eval vsim -assertfile $log_file testbench

I am facing the problem that ModelSim updates files only when it is being
closed.
I.e. the files are created but I can access them straight after the
simulation:

vsim -assertfile $log_file testbench
run &time
quit -sim

So if i run script one more time I am already able to access necessary
information, but I am looking for solution
to accomplish it in one go.
Am I missing something (some design,project closing, or probably ModelSim
settings )??
Thanks for help.

--
Alex

 

[Mike Treseler]

Alex wrote:

eval vsim -assertfile $log_file testbench

I am facing the problem that ModelSim updates files only when it is
being closed.

Modelsim will do whatever "testbench" tells it to do.

Am I missing something

The source to testbench?

-- Mike Treseler

 

[Alex]

ModelSim will do whatever "testbench" tells it to do.

Am I missing something

The source to testbench?

Sorry that I didn't make it clear in the initial massage, but I obviously
compile
both design and testbench files into 'work' library. In the instruction

eval vsim -assertfile $log_file testbench

"testbench" is the name of test bench entity.
ModelSim does everything fine, and after closing itself assert files are
what they suppose to be. But I am not able to access(for reading) them
during fulfilling
the script.

Just while writing this message I've noticed that additional design
loading resolve the problem, i.e.

eval vsim -assertfile $log_file testbench
eval vsim -assertfile $log_file testbench
run $time
quit -sim

if [ catch {open $log_file r} test_info] {
puts $errID "Error: $design Fail to open: $log_file ;"
} else {
...

I steel don't see the problem.



--
Alex

 

[Jonathan Bromley]

On Mon, 21 Nov 2005 21:15:05 -0000, Alex <al.lopich@gmail.com> wrote:

eval vsim -assertfile $log_file testbench

"testbench" is the name of test bench entity.
ModelSim does everything fine, and after closing itself assert files are
what they suppose to be. But I am not able to access(for reading) them
during fulfilling
the script.

I believe that ModelSim places an exclusive lock on files that it's
writing during simulation.

Just while writing this message I've noticed that additional design
loading resolve the problem, i.e.

eval vsim -assertfile $log_file testbench
eval vsim -assertfile $log_file testbench

Hmmm. I wonder if it's like this... when you run [vsim],
ModelSim creates a TEMPORARY file somewhere; then at the end of
sim, ModelSim RENAMES that file to whatever you specified as
$log_file. That would explain what's going on when you invoke
[vsim] twice: the second [vsim] kills the old simulation and
starts another, but renames the empty assertions file so
that you can see it.

Sorry I can't be more help. Have you tried Mentor (or distributor)
support?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Alex]

eval vsim -assertfile $log_file testbench
eval vsim -assertfile $log_file testbench

Hmmm. I wonder if it's like this... when you run [vsim],
ModelSim creates a TEMPORARY file somewhere; then at the end of
sim, ModelSim RENAMES that file to whatever you specified as
$log_file. That would explain what's going on when you invoke
[vsim] twice: the second [vsim] kills the old simulation and
starts another, but renames the empty assertions file so
that you can see it.

And then I use quit -sim and wait for a while with "after $time"

Sorry I can't be more help. Have you tried Mentor (or distributor)
support?

Support doesn't really help, and as I could see from the experience of
other
people it is a common problem.


--
Alex

 

[Alex]

Just wanted to add for those how are interested, that reply from Xilinx
regarding the mentioned about issue,
proved that this is just a bug in modelsim, and no way to overcome!

Hi guys,

I experience some problem with modeling some designs in ModelSim 5.7 XE
2/Starter trough Tcl script.

I have a set of designs with corresponding testbenches, and while
running simulations through

eval vsim -assertfile $log_file testbench

I am facing the problem that ModelSim updates files only when it is
being closed.
I.e. the files are created but I can access them straight after the
simulation:

vsim -assertfile $log_file testbench
run &time
quit -sim

So if i run script one more time I am already able to access necessary
information, but I am looking for solution
to accomplish it in one go.
Am I missing something (some design,project closing, or probably
ModelSim settings )??
Thanks for help.

--
Alex

--
Alex