Assertion based Verification

[Gokul]

I am not a complete newbie to Verilog but quite new to the industry
verification environments.
I am just puzzled by this term "Assertion based Verification" and dont
know how to decipher it.
I can understand what assertion means...It refers to a signal being
kept active for a certain period of time.
0 --> 1 transition of a particular signal and "the signal remaining at
logic 1" will be referred to as "the signal is kept asserted".

Is there any misconceptions in my understanding of assertions???
Please explain what this "Assertion based Verification" refers to and
its practical significance in chip design.

 

[Muzaffer Kal]

On Mon, 13 Oct 2008 01:28:32 -0700 (PDT), Gokul <gokul.bits@gmail.com>
wrote:

I am not a complete newbie to Verilog but quite new to the industry
verification environments.
I am just puzzled by this term "Assertion based Verification" and dont
know how to decipher it.
I can understand what assertion means...It refers to a signal being
kept active for a certain period of time.
0 --> 1 transition of a particular signal and "the signal remaining at
logic 1" will be referred to as "the signal is kept asserted".

Is there any misconceptions in my understanding of assertions???
Please explain what this "Assertion based Verification" refers to and
its practical significance in chip design.

The assertions in question are of a different kind. They're something
inherited from computer science where there is a contract between the
producer and consumer of a resource or a signal and assertions are
used to enforce this contract. One example would be that say the first
byte in the start of a packet would be the count and it would be less
than 10 so you can put in an assertion such as follows:

assert(first_byte && byte_val < 10);

This would generate an error in a log file or stop the simulation
depending on how assertions are configured.
You can define quite complicated assertions which can effectively
embed designers' intent and the protocol needed into the design
itself. Another extremely useful consequence of adding assertions to a
design is that it's possible to develop formal tools which can analyze
the producer side design and verify that it does indeed generate
transactions which would comply with the assertions on the consumer
side without even running simulations. Or make sure that if all the
assertions are conformed the consumer side would interpret the
incoming data/transactions without any other problems.
Muzaffer Kal
ASIC/FPGA Design Services
DSPIA INC.
http://www.dspia.com

 

[Sree]

On Oct 13, 8:16 pm, Muzaffer Kal <k...@dspia.com> wrote:

On Mon, 13 Oct 2008 01:28:32 -0700 (PDT), Gokul <gokul.b...@gmail.com
wrote:

I am not a complete newbie to Verilog but quite new to the industry
verification environments.
I am just puzzled by this term "Assertion based Verification" and dont
know how to decipher it.
I can understand what assertion means...It refers to a signal being
kept active for a certain period of time.
0 --> 1 transition of a particular signal and "the signal remaining at
logic 1" will be referred to as "the signal is kept asserted".

Is there any misconceptions in my understanding of assertions???
Please explain what this "Assertion based Verification" refers to and
its practical significance in chip design.

The assertions in question are of a different kind. They're something
inherited from computer science where there is a contract between the
producer and consumer of a resource or a signal and assertions are
used to enforce this contract. One example would be that say the first
byte in the start of a packet would be the count and it would be less
than 10 so you can put in an assertion such as follows:

assert(first_byte && byte_val < 10);

This would generate an error in a log file or stop the simulation
depending on how assertions are configured.
You can define quite complicated assertions which can effectively
embed designers' intent and the protocol needed into the design
itself. Another extremely useful consequence of adding assertions to a
design is that it's possible to develop formal tools which can analyze
the producer side design and verify that it does indeed generate
transactions which would comply with the assertions on the consumer
side without even running simulations. Or make sure that if all the
assertions are conformed the consumer side would interpret the
incoming data/transactions without any other problems.
Muzaffer Kal
ASIC/FPGA Design Services
DSPIA INC.http://www.dspia.com

Hi,

I have one more query on asssertions.
By having assertions, can we cut down on the stimulus that is required
to verify the design??