Assertin with delay (not clock cycles)

[Deepu]

Hi All,

Is there a way i can use assertion to check a condition like:

when posedge happens on signal A then check the value on signal B
changes to some other value after 43 ns. (clock cycle is 25ns)

I tried:

assert property ( @(posedge signalA) (signalB != 4'b0) |-> #43
(signalB == 4'b1111));

Can i try something like this? Which is the better way to use
assertion for this case.

Thanks..

 

[Jonathan Bromley]

On Fri, 1 Oct 2010 12:10:06 -0700 (PDT), Deepu wrote:

Is there a way i can use assertion to check a condition like:

when posedge happens on signal A then check the value on signal B
changes to some other value after 43 ns. (clock cycle is 25ns)

SystemVerilog assertions are clocked. End of story. So if you
want an assertion to do this, you must create a clock that
fires at the appropriate time(s).

I would question your underlying assumptions here. What is
the tolerance on your 43ns? It's ridiculous to demand that
the signal change after _exactly_ 43 ns. I assume that
what you really want is...
- there is no change on B for the first 40ns;
- after 46ns, B has its new value
or something like that - in other words, you want a time
window for stability and updating of B after the clock
on A.

You should look carefully at the Verilog built-in timing
checks such as $hold(). They are better suited to this
kind of measurement than assertions, which are designed
to handle RTL (zero-delay) functional behaviour.
--
Jonathan Bromley