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You can always check a value od signal with 'if' statement and reportAs a 'C' programmer, I am fond of using asserts - is there an equivalent in
Verilog so I can for example check for appropriate parameter values in my
modules? I have looked but the results were a little confusing.
"DW" <dave_wooff@hotmail.com> wrote in message
news:<c8agat$iu0$1$830fa79d@news.demon.co.uk>...
As a 'C' programmer, I am fond of using asserts - is there an equivalent
in
Verilog so I can for example check for appropriate parameter values in
my
modules? I have looked but the results were a little confusing.
You can always check a value od signal with 'if' statement and report
with '$display'.
You should however wrap it with preprocessor directive `ifdef cause it
is not synthesizable.
I experimented with XST. It merely ignored the $display, so there isThanks, I'll give this a try
"Nahum Barnea" <nahum_barnea@yahoo.com> wrote in message
news:fc23bdfc.0405171004.2594da86@posting.google.com...
"DW" <dave_wooff@hotmail.com> wrote in message
news:<c8agat$iu0$1$830fa79d@news.demon.co.uk>...
As a 'C' programmer, I am fond of using asserts - is there an equivalent
in
Verilog so I can for example check for appropriate parameter values in
my
modules? I have looked but the results were a little confusing.
You can always check a value od signal with 'if' statement and report
with '$display'.
You should however wrap it with preprocessor directive `ifdef cause it
is not synthesizable.
AFAIK all synth tools simply ignore $... system tasks.I experimented with XST. It merely ignored the $display, so there is
no need to use the preprocessor in that way.
What do other synthesisers do?
Yes, I was thinking of an assert which would raise an error whenOn Wed, 19 May 2004 12:32:27 +1000, Allan Herriman
allan.herriman.hates.spam@ctam.com.au.invalid> wrote:
I experimented with XST. It merely ignored the $display, so there is
no need to use the preprocessor in that way.
What do other synthesisers do?
AFAIK all synth tools simply ignore $... system tasks.
However, you still sometimes need `ifdef because you
often need to wrap your $display in a bit more logic
to do the assertion in the way you want.
SystemVerilog has a full-fledged assertion mechanism. It should
be pretty easy for tool vendors to support (==ignore, in synth)
those constructs, so I guess we'll see it supported quite soon.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
out of the question. Whether this is a good decision remains to be seen,On Thu, 20 May 2004 09:17:56 +0100, "DW"
dave_wooff@hotmail.com> wrote:
I was thinking of an assert which would raise an error when
synthesizing - not when simulating. Basically I want to
raise an error if a particular combination of (potentially
defparam overriden) parameter values is incorrect, so
there would be no point continuing with the compilation.
Consider using VHDL. I frequently use VHDL assertions for
exactly this purpose. It's a great approach, and synthesis
tools give you appropriate messages.
--
Jonathan Bromley, Consultant
We have made a decision to use Verilog for all new designs, so using VHDL is