assert false report "blah blah blah" severity note;

[A. Kong]

Hi, all,

I want to use the statment " assert false report "blah blah blah"
severity note;" as a way to print some information in ModelSim. However,
Xilinx, upon compiling the source, says:

Assertion st
atement ignored.


My questions are:
1) Is there any restriction on how to use assert statement? e.g. cannot
be used in process? if loop? Or is it just Xilinx?
2) Is there a better to print debug info? Utlimately I want to examine
the content of a region of memory...

Maybe I am not reading carefully but vhdl cookbook seems to only only
provide description of usage of assert.


Cheers,
Anthony

 

[Srinivasan Venkataramanan]

Hi,

"A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote in message
news:416a2152$1@duster.adelaide.on.net...

Hi, all,

I want to use the statment " assert false report "blah blah blah"
severity note;" as a way to print some information in ModelSim. However,
Xilinx, upon compiling the source, says:

Assertion st
atement ignored.

Assert stuff is meant for simulation only and hence during synthesis it is
ignored.

My questions are:
1) Is there any restriction on how to use assert statement? e.g. cannot
be used in process? if loop? Or is it just Xilinx?

I would say any synthesis tool.

2) Is there a better to print debug info? Utlimately I want to examine
the content of a region of memory...

You may want to try:

http://www.easics.com/webtools/freesics/PCK_FIO-2002.7

They have a neat printf like package. Also a google search for "printf vhdl
package" yielded: http://bear.ces.cwru.edu/vhdl/source/debugio_h.vhd

HTH,
Srinivasan
--
Srinivasan Venkataramanan
Corp. Appl. Engineer
Synopsys India Pvt. Ltd.
Bangalore, India
email:synopsys.com@svenkat
I own my words and not my employer, unless specifically mentioned

 

[Iwo Mergler]

A. Kong wrote:

Hi, all,

I want to use the statment " assert false report "blah blah blah"
severity note;" as a way to print some information in ModelSim. However,
Xilinx, upon compiling the source, says:

Assertion st
atement ignored.


My questions are:
1) Is there any restriction on how to use assert statement? e.g. cannot
be used in process? if loop? Or is it just Xilinx?
2) Is there a better to print debug info? Utlimately I want to examine
the content of a region of memory...

Maybe I am not reading carefully but vhdl cookbook seems to only only
provide description of usage of assert.


Cheers,
Anthony

If you just want to output a string in the simulator, use
report "Whatever" severity note. The assert is not necessary.
It should work for simulation. If you synthesize the design,
it gets indeed ignored.

Kind regards,

Iwo