ASMBL - hmmm

[Jim Granville]

Been following the rollout of
Application Specific Modular BLock (ASMBL) at Xilinx.
Lots of gushing words, but what is it REALLY ?

Thus far we can glean : Stripe layout, and areal bondpads
Not quite 'Revolutionary': Areal bondpads are nice to have,
and the Stripe layout has plus and minus columns :

Plus: Faster local speeds
Minus: Only to a certain ceiling
Plus: Faster Place/Route
Plus: Reduced routing cross points
Plus: Faster device Testing, & possible redundancy mapping
Plus: More consistant Place/Route migration
Minus: Tendancy to wastage : New IP -> New Column

CPLDs have been multiple-larger-block structured for years,
and Clock drivers on FPGAs are already have larger fabric
elements.

But more fun comes from what the analysts think all this means :

"I believe we'll eventually see FPGAs that are fully application-specific,"
said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is

a nice compromise without losing the economics of having an architecture
that can be used by multiple customers."

Er, isn't a 'fully application-specific FPGA' actually an ASIC ?

"If Xilinx is doing a chip that is 90% perfect for the app, the price
difference would have to be strong justification to make the leap into an

ASIC," Snyder said.

Might be that the more defined stripes make the move to Structured ASICs
easier, and
this 'MASK FPGA' segment would grow ?

Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?

-jg

 

[Steve Casselman]

They make it sound like it is a response to structured ASICs but it sounds a
little like the QuickSliver stuff to me. QS is embedding custom blocks along
with FPGA like blocks. Also the Structured ASICs are biting the dust but QS
has hired 50% of all the top reconfigurable computing people I have a lot of
faith in their abilities.

Steve


"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:EbrBb.12264$ws.1161156@news02.tsnz.net...

Been following the rollout of
Application Specific Modular BLock (ASMBL) at Xilinx.
Lots of gushing words, but what is it REALLY ?

Thus far we can glean : Stripe layout, and areal bondpads
Not quite 'Revolutionary': Areal bondpads are nice to have,
and the Stripe layout has plus and minus columns :

Plus: Faster local speeds
Minus: Only to a certain ceiling
Plus: Faster Place/Route
Plus: Reduced routing cross points
Plus: Faster device Testing, & possible redundancy mapping
Plus: More consistant Place/Route migration
Minus: Tendancy to wastage : New IP -> New Column

CPLDs have been multiple-larger-block structured for years,
and Clock drivers on FPGAs are already have larger fabric
elements.

But more fun comes from what the analysts think all this means :

"I believe we'll eventually see FPGAs that are fully
application-specific,"
said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this
is
a nice compromise without losing the economics of having an architecture
that can be used by multiple customers."

Er, isn't a 'fully application-specific FPGA' actually an ASIC ?

"If Xilinx is doing a chip that is 90% perfect for the app, the price
difference would have to be strong justification to make the leap into an
ASIC," Snyder said.

Might be that the more defined stripes make the move to Structured ASICs
easier, and
this 'MASK FPGA' segment would grow ?

Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?

-jg

 

[Austin Lesea]

Jim,

Now really, Jim, why so negative? Isn't Xilinx justified in rolling out
a new architecture with some fanfare? Why is it that others are allowed
to make outrageous and sometimes even false claims, and no one cares?
Yet when we announce a truely revolutionary FPGA architecture, we get
complaints?

If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that worth
shouting about?

More and more we see market specific applications that require a more
cost effective FPGA (eg software defined radio is a totally different
mix of features than automotive entertainment center). Why not be able
to target a general purpose device to a specific market segment at
reduced cost and better margins? Might get more business that way,
right? If Spartan 3 is already cost effective against many ASICs, might
this not make us even a better cost/benefit solution?

I do agree that the analysts do not have a clue, however. For example,
we are being compared to structured ASICs and other "hard" solutions.
Those are misleading and false. They are all dead-ends (just a re-spin
of gate arrays with new clothing, or some other ASIC flow with window
dressing liberally applied).

As for the details that I am sure you want to hear, you have to wait
until the next press release.

Schedule: architectual release, then specific family details, then
product announcement. Nothing new here. Been following the same
formula for many years. Happy New Year!

Austin

Jim Granville wrote:

Been following the rollout of
Application Specific Modular BLock (ASMBL) at Xilinx.
Lots of gushing words, but what is it REALLY ?

Thus far we can glean : Stripe layout, and areal bondpads
Not quite 'Revolutionary': Areal bondpads are nice to have,
and the Stripe layout has plus and minus columns :

Plus: Faster local speeds
Minus: Only to a certain ceiling
Plus: Faster Place/Route
Plus: Reduced routing cross points
Plus: Faster device Testing, & possible redundancy mapping
Plus: More consistant Place/Route migration
Minus: Tendancy to wastage : New IP -> New Column

CPLDs have been multiple-larger-block structured for years,
and Clock drivers on FPGAs are already have larger fabric
elements.

But more fun comes from what the analysts think all this means :


"I believe we'll eventually see FPGAs that are fully application-specific,"

said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is
a nice compromise without losing the economics of having an architecture
that can be used by multiple customers."

Er, isn't a 'fully application-specific FPGA' actually an ASIC ?


"If Xilinx is doing a chip that is 90% perfect for the app, the price

difference would have to be strong justification to make the leap into an
ASIC," Snyder said.

Might be that the more defined stripes make the move to Structured ASICs
easier, and
this 'MASK FPGA' segment would grow ?

Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ?

-jg

 

[Jim Granville]

"Austin Lesea" wrote

Jim,

Now really, Jim, why so negative?

I did not think I was negative on the engineering aspects ?
- I listed more pluses than minuses ?

Isn't Xilinx justified in rolling out a new architecture with some
fanfare?

Of course, but when the gush exceeds the hard data, expect some
analysts to get it wrong....

Why is it that others are allowed
to make outrageous and sometimes even false claims, and no one cares?
Yet when we announce a truely revolutionary FPGA architecture, we get
complaints?

"truely revolutionary" is a bold claim.

I can see good Engineering & Yield trade-offs in what's released so far, but
that's some way short of "truely revolutionary".

If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that worth
shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?
With real care, 'the mask' could even be effectively virtual by using
stripe based exposures at the wafer level.

Challenge there will be in the definition, to get devices to reach critical
mass, and
not go EOL as uptakes do not quite meet forecasts.

More and more we see market specific applications that require a more
cost effective FPGA (eg software defined radio is a totally different
mix of features than automotive entertainment center). Why not be able
to target a general purpose device to a specific market segment at
reduced cost and better margins? Might get more business that way,
right? If Spartan 3 is already cost effective against many ASICs, might
this not make us even a better cost/benefit solution?

So is this not a merchant market device, but an 'ASIC cherry pick' vehicle ?

-jg

 

[Peter Alfke]

Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.
Exactly what the company wants. We cannot yet offer this for sale, but
we can create some expectations.
As Austin said, wait for the next, more detailed disclosure.
Any similarity with strip-tease is purely intentional...

Peter
============================
Jim Granville wrote:

"Austin Lesea" wrote
Jim,

Now really, Jim, why so negative?

I did not think I was negative on the engineering aspects ?
- I listed more pluses than minuses ?

Isn't Xilinx justified in rolling out a new architecture with some
fanfare?

Of course, but when the gush exceeds the hard data, expect some
analysts to get it wrong....

Why is it that others are allowed
to make outrageous and sometimes even false claims, and no one cares?
Yet when we announce a truely revolutionary FPGA architecture, we get
complaints?

"truely revolutionary" is a bold claim.

I can see good Engineering & Yield trade-offs in what's released so far, but
that's some way short of "truely revolutionary".


If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that worth
shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?
With real care, 'the mask' could even be effectively virtual by using
stripe based exposures at the wafer level.

Challenge there will be in the definition, to get devices to reach critical
mass, and
not go EOL as uptakes do not quite meet forecasts.

More and more we see market specific applications that require a more
cost effective FPGA (eg software defined radio is a totally different
mix of features than automotive entertainment center). Why not be able
to target a general purpose device to a specific market segment at
reduced cost and better margins? Might get more business that way,
right? If Spartan 3 is already cost effective against many ASICs, might
this not make us even a better cost/benefit solution?

So is this not a merchant market device, but an 'ASIC cherry pick' vehicle ?

-jg

 

[Jim Granville]

"Peter Alfke" wrote

Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.
Exactly what the company wants. We cannot yet offer this for sale, but
we can create some expectations.
As Austin said, wait for the next, more detailed disclosure.
Any similarity with strip-tease is purely intentional...

Sounds like a new marketing manager fresh in from another industry.... ;-)

Even the technical press have taken the slightly misleading
"Xilinx Unveils Revolutionary..."
and watered it down to the more accurate
"Xilinx set to debut novel FPGA architecture"
"..set to debut in a 90nm Virtex device in the first half of 2004, segments
function blocks into interchangeable columns, rather than squares on a
grid."

-jg

 

[Austin Lesea]

Jim,

It is NOT "hard-to-copy"! Retains ALL of the reprogrammability and
functionality of a 'true' FPGA -- just does it for a better cost/benefit
trade-off.

"Hard-to-copy" means that if you make a mistake, you are toast. It is
inevitable that customers do not think of absolutely everything. The
new architecture will also allow us to provide EasyPath(tm), which if
the customer calls up (which has happened, and boy are they glad they
went with Xilinx!), and says "I forgot an inverter" we just modify the
test program, and they are back in business IMMEDIATELY, with only a
small charge (perhaps very small) for the modified test program work
that we have to do. No one else can do this, either! In fact,
EasyPath(tm) can be done for a few images (bistreams) and still retain
the savings. This fits it well with customers that wish to have single
platforms that perform multiple functions (ie cellular basestations
which are notorious for needing major changes every three months).

"Hard-to-copy" on a base station? Disaster. End of the world. Remember
I worked in telecom for 23 years, and FPGAs saved by rear-end so many
times, I can not count them all. Ever had a Class-A recall of 100,000
units from telephone companies? Nightmare. But if they are
reprogrammable, we only needed a seed stock of 1,000 units, and then
sent the new ones out, got back the old ones, reprogrammed them, and
went on thru the whole 100K. Saved the company. Saved the product.
Today you could send out a floppy, flash, or download it over the 'net.

That is why we state that "structured ASICs" are just a new description
for a "buggy whip" -- not even in the same century as what we are doing.

As for 'revolution', who has ever announced such a chip architecture?
Certainly no one in the FPGA industry. Haven't ever heard of it
anywhere else.

'Novel' is accurate as well. It is new. Prefer 'revolutionary', as
that implies a complete re-thinking, and introduction of radically new
benefits and features. The press announcement mentioned 100
innovations. That is no small feat for a new device family.

I suppose Peter and I are guilty of working here, but some of the things
that are coming up are awesome.......

Austin

Jim Granville wrote:

"Peter Alfke" wrote

Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.
Exactly what the company wants. We cannot yet offer this for sale, but
we can create some expectations.
As Austin said, wait for the next, more detailed disclosure.
Any similarity with strip-tease is purely intentional...


Sounds like a new marketing manager fresh in from another industry.... ;-)

Even the technical press have taken the slightly misleading
"Xilinx Unveils Revolutionary..."
and watered it down to the more accurate
"Xilinx set to debut novel FPGA architecture"
"..set to debut in a 90nm Virtex device in the first half of 2004, segments
function blocks into interchangeable columns, rather than squares on a
grid."

-jg

 

[Marc Randolph]

Howdy Austin,

Austin Lesea wrote:
[...]

"Hard-to-copy" means that if you make a mistake, you are toast. It is
inevitable that customers do not think of absolutely everything. The
new architecture will also allow us to provide EasyPath(tm), which if
the customer calls up (which has happened, and boy are they glad they
went with Xilinx!), and says "I forgot an inverter" we just modify the
test program, and they are back in business IMMEDIATELY, with only a
small charge (perhaps very small) for the modified test program work
that we have to do. No one else can do this, either! In fact,
EasyPath(tm) can be done for a few images (bistreams) and still retain
the savings. This fits it well with customers that wish to have single
platforms that perform multiple functions (ie cellular basestations
which are notorious for needing major changes every three months).

Hmmmm. If the customer is just changing the contents of a LUT, does
that really require requal'ing EasyPath parts and changing the test
program? My understanding of EasyPath was that components and routes
are tested, but I guess I don't have an exact definition of "component."
Could the contents of a LUT be changed without going through this
hassle? What about changing the polarity of a signal (or clk) going to
a flop? IOB parameters? Contents of a BRAM?

[...]

That is why we state that "structured ASICs" are just a new description
for a "buggy whip" -- not even in the same century as what we are doing.

And yet there are perfect applications for both buggy whips and
structured ASICs. Funny how an improvement on something doesn't
necessarily out date everything before it, isn't it?

As for 'revolution', who has ever announced such a chip architecture?
Certainly no one in the FPGA industry. Haven't ever heard of it
anywhere else.

'Novel' is accurate as well. It is new. Prefer 'revolutionary', as
that implies a complete re-thinking, and introduction of radically new
benefits and features. The press announcement mentioned 100
innovations. That is no small feat for a new device family.

Where I work, whenever we hear the word "revolution," our ears perk up.
Because we know that that history has shown that most real revolutions
fail, or at least, the first couple attempts at the revolution do. Both
old history and recent history, in all areas, from politics to the
telecom world, to the semiconductor world. It is VERY rare. So if I
were you, I'd personally shy away from that term unless it truly is
revolutionary, in which case, as a shareholder, I hope you're not
betting too much on it.

I am not saying I'm against revolutions when they are really called for.
I'm just saying that the word has been associated with A LOT of
failure and that whenever I hear it coming from the mouth of a marketing
droid, I hold onto my wallet.

I suppose Peter and I are guilty of working here, but some of the things
that are coming up are awesome.......

Indeed they are. It is a very exciting time for FPGAs, semiconductors,
and electronics in general. But just like we don't blame you for
talking up Xilinx, don't blame us for trying to keep the marketers in
check with all the fluff (and few details) they put out.

Have fun,

Marc

 

[Peter Alfke]

Jim, here are some fictitious press releases that might be to your taste:

Boeing 747: like a 727, just bigger
Porsche 911: like a VW, just faster
Nokia cell phone: like a Walkie-Talkie, just lighter
Transistor: like a vacuum tube, just smaller
LCD display: like a CRT, just flatter
FPGA: like a CPLD, just more complex

Any spectacular innovation can be de-dramatized.
Wouldn't excite any magazine editor, though.
Peter Alfke


Jim Granville wrote:

"Peter Alfke" wrote
Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.
Exactly what the company wants. We cannot yet offer this for sale, but
we can create some expectations.
As Austin said, wait for the next, more detailed disclosure.
Any similarity with strip-tease is purely intentional...

Sounds like a new marketing manager fresh in from another industry.... ;-)

Even the technical press have taken the slightly misleading
"Xilinx Unveils Revolutionary..."
and watered it down to the more accurate
"Xilinx set to debut novel FPGA architecture"
"..set to debut in a 90nm Virtex device in the first half of 2004, segments
function blocks into interchangeable columns, rather than squares on a
grid."

-jg

 

[Austin Lesea]

Marc,

--snip--

Hmmmm. If the customer is just changing the contents of a LUT, does
that really require requal'ing EasyPath parts and changing the test
program? My understanding of EasyPath was that components and routes
are tested, but I guess I don't have an exact definition of "component."
Could the contents of a LUT be changed without going through this
hassle? What about changing the polarity of a signal (or clk) going to
a flop? IOB parameters? Contents of a BRAM?

If they use a LUTRAM, SRL16, BRAM, then those features are 100% tested.

If they do not use a clock inversion, or do not use a different IO
standard, then these are not tested.

[...]

That is why we state that "structured ASICs" are just a new
description for a "buggy whip" -- not even in the same century as what
we are doing.


And yet there are perfect applications for both buggy whips and
structured ASICs. Funny how an improvement on something doesn't
necessarily out date everything before it, isn't it?

Oh yes. I have a buggy whip at home. Use it all of the time. Right.

As for 'revolution', who has ever announced such a chip architecture?
Certainly no one in the FPGA industry. Haven't ever heard of it
anywhere else.


'Novel' is accurate as well. It is new. Prefer 'revolutionary', as
that implies a complete re-thinking, and introduction of radically new
benefits and features. The press announcement mentioned 100
innovations. That is no small feat for a new device family.

Where I work, whenever we hear the word "revolution," our ears perk up.
Because we know that that history has shown that most real revolutions
fail, or at least, the first couple attempts at the revolution do. Both
old history and recent history, in all areas, from politics to the
telecom world, to the semiconductor world. It is VERY rare. So if I
were you, I'd personally shy away from that term unless it truly is
revolutionary, in which case, as a shareholder, I hope you're not
betting too much on it.

I am not saying I'm against revolutions when they are really called for.
I'm just saying that the word has been associated with A LOT of failure
and that whenever I hear it coming from the mouth of a marketing droid,
I hold onto my wallet.

Most revolutions fail? Hmmm. I suppose you also belong to the "glass
is half empty crowd."

Austin

 

[Peter Alfke]

Marc Randolph wrote:

I am not saying I'm against revolutions when they are really called for.
I'm just saying that the word has been associated with A LOT of
failure and that whenever I hear it coming from the mouth of a marketing
droid, I hold onto my wallet.

Fear of revolution?
Let's stay away from politics, and look at technology:

Programmable logic was a revolutionary idea (Signetics, MMI, Xilinx)
FM radio, LCD display, the PC/Mac, transistors, the printed circuit
board, the idea of a stored-program computer, telephony, radio, etc are
all revolutionary and successful ideas in electronics.

The 4-stroke gasoline (Otto) and Diesel, and jet engines, powered flight
(Wright), movable type (Gutenberg) were all revolutionary inventions
that caught on extremely fast. Vaccination and recent progress in
medicine must be called revolutionary. (Nice not to worry about polio
anymore). DNA testing in law enforcement...

Let's keep at least some of the enthusiasm for scientific progress that
permeated my youth, long ago.

Let's hear it for revolution again! Down with pessimism and sarcasm !
Peter Alfke

 

[Jim Granville]

"Peter Alfke" wrote

Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.

Maybe - I'm still trying to cut through the fluff, to make my own mind up.

"Austin Lesea" wrote
Jim,
If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that
worth
shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?

One poor aspect of the info so far, is it does not delineate SOFT and HARD
features clearly at all.
So, I am trying to see what is new, or clever, and may be over-interpreting
some info....

Putting the discussion of 'revolution' to one side, can we focus on
what really is new, or clever ?

My reading of the fluff so far, is that there is some freedom to
stripe-select at
FAB time, and so Xilinx can roll new die variants relatively easily to
target
new market segments - correct, or not ?

Now, if that really is a whole new mask set, then that will have
significant
NRE costs, esp at 90nm, and so restrict the market reach, but I could
imagine
a smarter-flow where the stripes are 'printed a stripe at a time', and this
would
slash NRE to an admin/package/test flow aspect.
Q: Which of these applies to 'the mask' ?

-jg

 

[Austin Lesea]

Jim,

---snip---

... there is some freedom to
stripe-select at
FAB time, and so Xilinx can roll new die variants relatively easily to
target
new market segments - correct, or not ?

Correct.



The rest has to wait for the next press release.

Austin

 

[Peter Alfke]

Jim, it's best to stop reading too much into the press release. We
should never even have mentioned stripes and soft and hard, it just
sends smart guys like you off in strange directions.

Let's keep it at:
Xilinx will soon announce a new and exciting, fast and flexible
architecture. Stay tuned, you will like it.
You can decide later whether it is evolutionary or revolutionary.
Trust me, it's both...
End of story, for the time being.

Peter Alfke
======================
Jim Granville wrote:

"Peter Alfke" wrote
Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.

Maybe - I'm still trying to cut through the fluff, to make my own mind up.

"Austin Lesea" wrote
Jim,
If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that
worth
shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?

One poor aspect of the info so far, is it does not delineate SOFT and HARD
features clearly at all.
So, I am trying to see what is new, or clever, and may be over-interpreting
some info....

Putting the discussion of 'revolution' to one side, can we focus on
what really is new, or clever ?

My reading of the fluff so far, is that there is some freedom to
stripe-select at
FAB time, and so Xilinx can roll new die variants relatively easily to
target
new market segments - correct, or not ?

Now, if that really is a whole new mask set, then that will have
significant
NRE costs, esp at 90nm, and so restrict the market reach, but I could
imagine
a smarter-flow where the stripes are 'printed a stripe at a time', and this
would
slash NRE to an admin/package/test flow aspect.
Q: Which of these applies to 'the mask' ?

-jg

 

[rickman]

Hey, I'd be happy if they get their current hardware and software to
operate fully.



Peter Alfke wrote:

Jim, it's best to stop reading too much into the press release. We
should never even have mentioned stripes and soft and hard, it just
sends smart guys like you off in strange directions.

Let's keep it at:
Xilinx will soon announce a new and exciting, fast and flexible
architecture. Stay tuned, you will like it.
You can decide later whether it is evolutionary or revolutionary.
Trust me, it's both...
End of story, for the time being.

Peter Alfke
======================
Jim Granville wrote:

"Peter Alfke" wrote
Jim,
this was the first pre-announcement of something new from Xilinx. Don't
complain that it is vague, it is meant to be. It's supposed to create
interest, curiosity, perhaps even impatient excitement.

Maybe - I'm still trying to cut through the fluff, to make my own mind up.

"Austin Lesea" wrote
Jim,
If we can architect a device to allow for any collection of "stripes"
and have the mask, and the software ready immediately, isn't that
worth
shouting about?

Can you clarify 'the mask' ?
Does this mean this will become like a block-hard-copy (but still FPGA),
where a large enough customer (/market?) can 'select the mix of stripes'
and a new die results ?

One poor aspect of the info so far, is it does not delineate SOFT and HARD
features clearly at all.
So, I am trying to see what is new, or clever, and may be over-interpreting
some info....

Putting the discussion of 'revolution' to one side, can we focus on
what really is new, or clever ?

My reading of the fluff so far, is that there is some freedom to
stripe-select at
FAB time, and so Xilinx can roll new die variants relatively easily to
target
new market segments - correct, or not ?

Now, if that really is a whole new mask set, then that will have
significant
NRE costs, esp at 90nm, and so restrict the market reach, but I could
imagine
a smarter-flow where the stripes are 'printed a stripe at a time', and this
would
slash NRE to an admin/package/test flow aspect.
Q: Which of these applies to 'the mask' ?

-jg

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Hal Murray]

"Hard-to-copy" means that if you make a mistake, you are toast. It is
inevitable that customers do not think of absolutely everything. The
new architecture will also allow us to provide EasyPath(tm), which if
the customer calls up (which has happened, and boy are they glad they
went with Xilinx!), and says "I forgot an inverter" we just modify the
test program, and they are back in business IMMEDIATELY, with only a
small charge (perhaps very small) for the modified test program work
that we have to do. No one else can do this, either! In fact,
EasyPath(tm) can be done for a few images (bistreams) and still retain
the savings. This fits it well with customers that wish to have single
platforms that perform multiple functions (ie cellular basestations
which are notorious for needing major changes every three months).

I don't understand that. I assume we are discussing saving $ by
only testing the parts of the chip that will be used rather than
the whole thing.

If the base stations are changing every three months, are they just
switching between a small collection of choices that are known
ahead of time, or are they rolling out new features?

If they are rolling out new features, then they are probably making
interesting changes to the FPGA code and probably would want the
fully tested version rather than the cheaper one that might not run
the new code.


I like the idea of saving money, but I've never worked on gear
that didn't get fixed/upgraded in the field.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Austin Lesea]

Hal,

To use EasyPath(tm) one has to have a stable design, or a set of stable
designs (like 3 designs). If you want to upgrade designs in the field,
then you might be in trouble, just as you point out.

You are not 100% guaranteed to be in trouble, but the yield of a new
untried pattern to a set of EasyPath product will not be 100%. It will
not be less than about 90 or 95% either, based on our tests and research.

For some that is acceptable. For others, not. In any event,
"Hard-to-copy" offers no ability to change at all, so there is no
comparison. There is a 100% guarantee of returning and replacing all
parts and boards if there is a required change.

If I am trying to manage my risks, 10% failure vs 100% failure is a big
factor.

Nothing is perfect, but we strive to get the best fit for the customer
with our product offerings.

Austin

Hal Murray wrote:

"Hard-to-copy" means that if you make a mistake, you are toast. It is
inevitable that customers do not think of absolutely everything. The
new architecture will also allow us to provide EasyPath(tm), which if
the customer calls up (which has happened, and boy are they glad they
went with Xilinx!), and says "I forgot an inverter" we just modify the
test program, and they are back in business IMMEDIATELY, with only a
small charge (perhaps very small) for the modified test program work
that we have to do. No one else can do this, either! In fact,
EasyPath(tm) can be done for a few images (bistreams) and still retain
the savings. This fits it well with customers that wish to have single
platforms that perform multiple functions (ie cellular basestations
which are notorious for needing major changes every three months).


I don't understand that. I assume we are discussing saving $ by
only testing the parts of the chip that will be used rather than
the whole thing.

If the base stations are changing every three months, are they just
switching between a small collection of choices that are known
ahead of time, or are they rolling out new features?

If they are rolling out new features, then they are probably making
interesting changes to the FPGA code and probably would want the
fully tested version rather than the cheaper one that might not run
the new code.


I like the idea of saving money, but I've never worked on gear
that didn't get fixed/upgraded in the field.

 

[jim granville]

Hal Murray wrote:
I don't understand that. I assume we are discussing saving $ by
only testing the parts of the chip that will be used rather than
the whole thing.

If the base stations are changing every three months, are they just
switching between a small collection of choices that are known
ahead of time, or are they rolling out new features?

If they are rolling out new features, then they are probably making
interesting changes to the FPGA code and probably would want the
fully tested version rather than the cheaper one that might not run
the new code.


I like the idea of saving money, but I've never worked on gear
that didn't get fixed/upgraded in the field.
Austin Lesea wrote:
Hal,

To use EasyPath(tm) one has to have a stable design, or a set of stable
designs (like 3 designs). If you want to upgrade designs in the field,
then you might be in trouble, just as you point out.

You are not 100% guaranteed to be in trouble, but the yield of a new
untried pattern to a set of EasyPath product will not be 100%. It will
not be less than about 90 or 95% either, based on our tests and research.

Is this 90-95% based on a complete new pattern, or some small respin of
the known good design ?

For some that is acceptable. For others, not. In any event,
"Hard-to-copy" offers no ability to change at all, so there is no
comparison. There is a 100% guarantee of returning and replacing all
parts and boards if there is a required change.

If I am trying to manage my risks, 10% failure vs 100% failure is a big
factor.

Nothing is perfect, but we strive to get the best fit for the customer
with our product offerings.

Austin

Interesting numbers.
This does point to some usefull tool features :
1) Ability to reuse as much existing place/route in a change as possible
( even to the point of less optimum results )
2) Ability to create multiple, seeded changes to a design.
- ie if your design change can hold 98% of previous proven/tested
place/route and give, say 3 version of the 2% 'fix', then in a expensive
HW situation you could try these 3, and choose the one that works.
3) Ability to place idle-test-patterns, into spare resource areas, with
a view to giving some test coverage.

It's all more work, but does give a satistical method to reduce the
non-zero chance of 'must change HW', esp if that HW change is very costly.

Reminds me of a story I heard about the very first Russian embedded uC,
(military) where production came serialised with a list of which opcodes
did not work, and the designers task was to code around that list.
(Intel tried a similar path with their Pentium a while ago !
-jg

 

[Austin Lesea]

Jim,

The coverage (?) of a completely new and different pattern is about 90
to 95%.

That is just because about 90 to 95% of any FPGA is unused (really, just
count the number of bits set to a '1').

The overlap of bits that change from one design to the next is probably
so random, that there is not much use in trying to keep track.

Austin

jim granville wrote:

Hal Murray wrote:
I don't understand that. I assume we are discussing saving $ by
only testing the parts of the chip that will be used rather than
the whole thing.

If the base stations are changing every three months, are they just
switching between a small collection of choices that are known
ahead of time, or are they rolling out new features?

If they are rolling out new features, then they are probably making
interesting changes to the FPGA code and probably would want the
fully tested version rather than the cheaper one that might not run
the new code.


I like the idea of saving money, but I've never worked on gear
that didn't get fixed/upgraded in the field.
Austin Lesea wrote:

Hal,

To use EasyPath(tm) one has to have a stable design, or a set of
stable designs (like 3 designs). If you want to upgrade designs in
the field, then you might be in trouble, just as you point out.

You are not 100% guaranteed to be in trouble, but the yield of a new
untried pattern to a set of EasyPath product will not be 100%. It
will not be less than about 90 or 95% either, based on our tests and
research.


Is this 90-95% based on a complete new pattern, or some small respin of
the known good design ?


For some that is acceptable. For others, not. In any event,
"Hard-to-copy" offers no ability to change at all, so there is no
comparison. There is a 100% guarantee of returning and replacing all
parts and boards if there is a required change.

If I am trying to manage my risks, 10% failure vs 100% failure is a
big factor.

Nothing is perfect, but we strive to get the best fit for the customer
with our product offerings.

Austin


Interesting numbers.
This does point to some usefull tool features :
1) Ability to reuse as much existing place/route in a change as possible
( even to the point of less optimum results )
2) Ability to create multiple, seeded changes to a design.
- ie if your design change can hold 98% of previous proven/tested
place/route and give, say 3 version of the 2% 'fix', then in a expensive
HW situation you could try these 3, and choose the one that works.
3) Ability to place idle-test-patterns, into spare resource areas, with
a view to giving some test coverage.

It's all more work, but does give a satistical method to reduce the
non-zero chance of 'must change HW', esp if that HW change is very costly.

Reminds me of a story I heard about the very first Russian embedded uC,
(military) where production came serialised with a list of which opcodes
did not work, and the designers task was to code around that list.
(Intel tried a similar path with their Pentium a while ago !
-jg

 

[acm]

Easypath = EasyScrap...

Hey, buy our excess scrapped inventory!!!!