H
H.Azmi
Guest
what can cause this error :
ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
???
ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
???
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U
Uwe Bonnes
Guest
H.Azmi <haythamazmi@hotmail.com> wrote:
: what can cause this error :
: ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
You overwhelm us with information.
Do you do schematic capture for your design?
I guess you connected some gate output to ground.
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
: what can cause this error :
: ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
You overwhelm us with information.
Do you do schematic capture for your design?
I guess you connected some gate output to ground.
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
J
John Adair
Guest
I have seen similar things generated by synthesisers When this has been the
problem the net is driven by the output of a lut. The lut has a constant
value output and has no inputs. To find if this is the problem use FPGA
EDITOR to look at the design, select the net from the list window and use
the attrib button to bring up the pop-up window. Then select the pins tab
and you will see the output and inputs of the net.
If this is your problem check to see if you are synthesising for the correct
part. This sort of structure is sometimes valid in families without built-in
pull elements. Otherwise try and change your logic, or synth options, to get
a different synthesis that might not have the problem.
John Adair
Enterpoint Ltd.
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"H.Azmi" <haythamazmi@hotmail.com> wrote in message
news:34c5542c.0401280550.78f8ee0e@posting.google.com...
problem the net is driven by the output of a lut. The lut has a constant
value output and has no inputs. To find if this is the problem use FPGA
EDITOR to look at the design, select the net from the list window and use
the attrib button to bring up the pop-up window. Then select the pins tab
and you will see the output and inputs of the net.
If this is your problem check to see if you are synthesising for the correct
part. This sort of structure is sometimes valid in families without built-in
pull elements. Otherwise try and change your logic, or synth options, to get
a different synthesis that might not have the problem.
John Adair
Enterpoint Ltd.
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"H.Azmi" <haythamazmi@hotmail.com> wrote in message
news:34c5542c.0401280550.78f8ee0e@posting.google.com...
what can cause this error :
ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
???
M
Mike Treseler
Guest
H.Azmi wrote:
-- Mike Treseler
http://groups.google.com/groups?q=gnd+net+driven+primitive+gate+vhdlERROR: a gnd net is driven by primitive gate(s) -- NET: GND0
-- Mike Treseler