M
mike0109
Guest
(1) I need to prototype Arm A5 processor in Xilinx V7 2000 FPGA. A5 has AXI bus and Xilinx supports DDR3 Controller+AXI bus using Core gen. Thus I can actually use the DRAM with A5 in FPGA. The thing is that in our actual ASIC, we are using different DDR3/DDR4 memroy controller that has different set of DRAM registers. From software development side I need to be able to support these registers in Xilinx. Is it possible to modify the Xilinx Coregen generated Verilog DDR3 controller significantly? Or do I need to have separate wrapper between the ARM core and DDR3 memory controller on AXI bus?
(2) Also linting tools like vavlog and vaelab may not be valid for FPGA. In that case what are the RTL linting tools which we have to run for qualifying ASIC RTL for FPGA
(3) I am thinking that the FPGA V72000 is big enough to support both the A5, DDR3 memory controller and other devices such SPI, I2C and possibly PCIe. I am not sure if I need to paritition this in multiple FPGAs.
(4) Is the Chipscope still the best way to get visibility into the design and debug? Or is there a better solution?
(5) If I am not concerned about performance, I am not sure how much time should I allocate for this type of task? Is it 3 month effort? I have done some FPGA development using both Altera and Xilinx
Prompt response is greatly appreciated.
(2) Also linting tools like vavlog and vaelab may not be valid for FPGA. In that case what are the RTL linting tools which we have to run for qualifying ASIC RTL for FPGA
(3) I am thinking that the FPGA V72000 is big enough to support both the A5, DDR3 memory controller and other devices such SPI, I2C and possibly PCIe. I am not sure if I need to paritition this in multiple FPGAs.
(4) Is the Chipscope still the best way to get visibility into the design and debug? Or is there a better solution?
(5) If I am not concerned about performance, I am not sure how much time should I allocate for this type of task? Is it 3 month effort? I have done some FPGA development using both Altera and Xilinx
Prompt response is greatly appreciated.