ASIC core question

Is it OK to instantiate glue logic such as mux at core level of ASIC?
If not, what's the benifit of moving those mux into one of sub modules?

 

[Berty]

Generally speaking it is ok to do anything you want as long as the
company who do for you the Fab/synthesis etc accept it.

Usually however assume you are only doing the RTL part you want to have
your code written in your own module with your own logic etc.

Than all those modules will be instantiate in a core file
The core file will be instantiate by the Jtag file
And the Jtag file will be instantiate by the top file.

All your tri-state should be in the top level where you will also
instantiate the PLL's you might have, and reset IO handler.

And sometime you will be asked to move your memory to the core level
(make life easier when adding the BIST part) so if they are buried in
"deep" modules you might be asked to move them up again depend with
whom you work.

To the hierarchy will look like

top_module_top ->
pll's_module
IO_reset_module
tri-state IO's.
top_modeule_jtag ->
jtag_core (usually will be added later by the company you work with)
top_module_core ->
submodule_abc
submodule_def
memory_111 (usually will be change later to one with BIST)
memory_222 (usually will be change later to one with BIST)

Of course there are few other issue like scan etc as well as even this
is more of a "guide" as almost all will accept some logic in the
core level as it is not a "Forbidden" rule, just preference and
"clean code".

Also a small suggestion if you have synchronizer make sure to use a
unique name for the two FF's and in particular the first one as it
will help you when you get to run post place and route simulation.

Have fun.