Artix-7 tools, ISE vs Vivado

[Vladimir Ivanov]

Hello,

What are the practical pros and cons of using each of ISE or Vivado for
the Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside from
possible speed increase in Vivado, do the synthesis/map/route perform
better by generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning Vivado in
the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx
families, so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

Thanks,
-- Vlad

 

[Mark Curry]

In article <alpine.DEB.2.02.1501272109300.5159@zztop.nucleusys.com>,
Vladimir Ivanov <vladitx@nucleusys.com> wrote:

Hello,

What are the practical pros and cons of using each of ISE or Vivado for
the Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside from
possible speed increase in Vivado, do the synthesis/map/route perform
better by generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning Vivado in
the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx
families, so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

Vladimir,

I'm in the same boat as you - supporting both "7 series" and above
devices, and older Xilinx technologies. Only certain 7-series devices
allow you the option of ISE or vivado, so a lot of the time the
decision is made for you.

I did use one of the devices where we had a choice - migrating a Virtex
6, to a Kintex 7. At first, to maintain our flows we went with ISE.
After getting our Vivado flows clean (which took WAY more time than it
should have, but that's another story..), We're now using Vivado. The
QOR is MUCH better - both better run times, and better timing results.
Many of our designs which had great difficulty meeting timing with ISE,
went through first time in Vivado and worked.

The TCL flows are more powerful. The constraint format - XDC files -
is leaps and bounds better than UCF (ugh.), but not without warts.

Once you get used to it, and setup your flows, you won't look back.

For the most part, we don't have to kludge up many of our source RTL
files to work with either ISE or Vivado. There's a few exceptions,
but nothing big.

Regards,

Mark

 

[Tom Gardner]

On 27/01/15 19:23, Vladimir Ivanov wrote:

Hello,

What are the practical pros and cons of using each of ISE or Vivado for the
Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside from
possible speed increase in Vivado, do the synthesis/map/route perform better by
generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning Vivado in the
context of Artix-7 only. No Zynq plans so far. I also use older Xilinx families,
so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

My impression, and that is all it is, is that ISE has reached the
end of the road and Vivado is the future. That seems reasonable
for tomorrows even larger devices, Zynq or otherwise.

Hence staying using ISE is likely to be limiting in the long run.

 

[Vladimir Ivanov]

On Tue, 27 Jan 2015, Tom Gardner wrote:

On 27/01/15 19:23, Vladimir Ivanov wrote:

Hello,

What are the practical pros and cons of using each of ISE or Vivado
for the
Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside
from
possible speed increase in Vivado, do the synthesis/map/route perform
better by
generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning
Vivado in the
context of Artix-7 only. No Zynq plans so far. I also use older Xilinx
families,
so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

My impression, and that is all it is, is that ISE has reached the
end of the road and Vivado is the future. That seems reasonable
for tomorrows even larger devices, Zynq or otherwise.

Hence staying using ISE is likely to be limiting in the long run.

True, but for anything older than the 7 series (Spartan and CPLDs) ISE is
the only choice, so it will be around for a long time, too. Except if a
miracle happens.

 

[Vladimir Ivanov]

On Tue, 27 Jan 2015, Mark Curry wrote:

In article <alpine.DEB.2.02.1501272109300.5159@zztop.nucleusys.com>,
Vladimir Ivanov <vladitx@nucleusys.com> wrote:

Hello,

What are the practical pros and cons of using each of ISE or Vivado for
the Artix-7 family?

I am interested in the basic synthesis/map/routing/STA steps. Aside from
possible speed increase in Vivado, do the synthesis/map/route perform
better by generating smaller and/or faster logic?

In general, my question is whether it's really worth it learning Vivado in
the context of Artix-7 only. No Zynq plans so far. I also use older Xilinx
families, so sticking to ISE is justified.

Any personal comparison between the two tools is also very welcome.

Vladimir,

I'm in the same boat as you - supporting both "7 series" and above
devices, and older Xilinx technologies. Only certain 7-series devices
allow you the option of ISE or vivado, so a lot of the time the
decision is made for you.

I did use one of the devices where we had a choice - migrating a Virtex
6, to a Kintex 7. At first, to maintain our flows we went with ISE.
After getting our Vivado flows clean (which took WAY more time than it
should have, but that's another story..), We're now using Vivado. The
QOR is MUCH better - both better run times, and better timing results.
Many of our designs which had great difficulty meeting timing with ISE,
went through first time in Vivado and worked.

The TCL flows are more powerful. The constraint format - XDC files -
is leaps and bounds better than UCF (ugh.), but not without warts.

Once you get used to it, and setup your flows, you won't look back.

For the most part, we don't have to kludge up many of our source RTL
files to work with either ISE or Vivado. There's a few exceptions,
but nothing big.

Hello Mark,

And thanks for the summary. It covers my expectations that switching to
Vivado will require extra time for getting used to, and then some for the
not so negligible unpolished pieces. The latter, being unpredictable, was
holding me mostly. With the heads up, I might as well give it a shot.

-- Vlad