arrays of wires

[raarce@gmail.com]

Hello:
I am new to the verilog language (I am familiar with VHDL). I got some
code of a website that seems to use arrays of wires. I have tried
compiling in ActiveHDL and Synplify and they don't seem to support this
type of structure. Is this structure valid in Verilog at all?

Here is a piece of the code...

parameter width = 8;

wire [width-1:0] x0_r [15:0];

Thanks,
Rafael

 

[John_H]

The wire array structure is not valid in Verilog.
The structure *is* valid in Verilog 2001.
Synplify has a checkbox in the Verilog Compiler configuration to use Verilog
2001 (at least the versions over the last year or two); I don't know about
ActiveHDL.

<raarce@gmail.com> wrote in message
news:1124488957.780114.251330@g49g2000cwa.googlegroups.com...

Hello:
I am new to the verilog language (I am familiar with VHDL). I got some
code of a website that seems to use arrays of wires. I have tried
compiling in ActiveHDL and Synplify and they don't seem to support this
type of structure. Is this structure valid in Verilog at all?

Here is a piece of the code...

parameter width = 8;

wire [width-1:0] x0_r [15:0];

Thanks,
Rafael