Arrays of buses

[Mark Brehob]

Hello,
I have a student who is trying to use arrays of buses, something we
normally recommend against.

He asks:
====================================================
We want to initialize an array of registers to some value during
reset. However, it's not working out. Here is what I have:
<code>
reg [6:0] i;
reg [63:0] foo[63:0];
reg [63:0] bar;
always @(posedge clock)
begin
if (reset)
begin
for(i=0; i<64; i=i+1)
begin
foo <= `SD 64'hdeadbeefbaadbeef; //Initialize to bogus
value
bar <= `SD 0; //Initialize to zero
end
end
end
</code>
So when I look at the waveform in make int, bar would be initialized
to all 0's, however, foo gets "NA". I think I'm not doing the array
indexing right. I want each of the 64 foo's to get the bogus value.
Any help would be awesome.
=======================================

we are using fairly new versions/updates of vcs and design compiler.
He's having problems even outside of synthesis, which seems odd. Any
thoughts/ideas? What are we missing here?

We've got it working _other_ than reset fairly well. Just this reset
thing is causing problems.

Thanks very much,
Mark

 

[John_H]

Usually resets get coded as asynchronous resets: always @(posedge clock or
posedge reset) but synchronous can work as well.
The initializations are shown but it's not obvious if foo is in the else
side of the if(reset) block.
If the foo assignment is in a different always block, there's a conflict:
apply the reset or the other assignment at the posedge clock?
If the foo assignment is in the else half of the if(reset) and there is a
clock edge during the reset, the initialization should be golden.

"Mark Brehob" <brehob@gmail.com> wrote in message
news:1172166364.855274.281220@q2g2000cwa.googlegroups.com...

Hello,
I have a student who is trying to use arrays of buses, something we
normally recommend against.

He asks:
====================================================
We want to initialize an array of registers to some value during
reset. However, it's not working out. Here is what I have:
code
reg [6:0] i;
reg [63:0] foo[63:0];
reg [63:0] bar;
always @(posedge clock)
begin
if (reset)
begin
for(i=0; i<64; i=i+1)
begin
foo <= `SD 64'hdeadbeefbaadbeef; //Initialize to bogus
value
bar <= `SD 0; //Initialize to zero
end
end
end
/code
So when I look at the waveform in make int, bar would be initialized
to all 0's, however, foo gets "NA". I think I'm not doing the array
indexing right. I want each of the 64 foo's to get the bogus value.
Any help would be awesome.
=======================================

we are using fairly new versions/updates of vcs and design compiler.
He's having problems even outside of synthesis, which seems odd. Any
thoughts/ideas? What are we missing here?

We've got it working _other_ than reset fairly well. Just this reset
thing is causing problems.

Thanks very much,
Mark

 

[Mark Brehob]

Thanks John,

On Feb 22, 3:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

Usually resets get coded as asynchronous resets: always @(posedge clock or
posedge reset) but synchronous can work as well.

Yeah, we avoid async resets mainly because someone always ends up
driving them with
combinational logic and gets killed by glitches.

The initializations are shown but it's not obvious if foo is in the else
side of the if(reset) block.
It is (conditionally) the actual code is:

('SD is just #1, it stands for "Standard Delay")
===========================
// synopsys sync_set_reset "reset"
always @(posedge clock)
begin
if (reset)
begin
for (i=0; i<64; i=i+1)
begin
registers <= `SD 64'hdeadbeefbaadbeef;
free_list <= `SD `NOT_FREE;
valid_list <= `SD `NOT_VALID;
end
end
else
begin
if(wr_en )
begin
registers[wr_prn] <= `SD value_in;
if (valid_in)
valid_list[wr_prn] <= `SD `VALID;
end
end
end
===========================

If the foo assignment is in a different always block, there's a conflict:
apply the reset or the other assignment at the posedge clock?
Nope, this is the only block it is assigned in.

It also isn't an input or output from the module.

If the foo assignment is in the else half of the if(reset) and there is a
clock edge during the reset, the initialization should be golden.
Yeah, I thought so too. I'll try messing around with it some more.

Anyone else have any ideas?

Thanks!

Mark

"Mark Brehob" <bre...@gmail.com> wrote in message

news:1172166364.855274.281220@q2g2000cwa.googlegroups.com...

Hello,
I have a student who is trying to use arrays of buses, something we
normally recommend against.

He asks:
====================================================
We want to initialize an array of registers to some value during
reset. However, it's not working out. Here is what I have:
code
reg [6:0] i;
reg [63:0] foo[63:0];
reg [63:0] bar;
always @(posedge clock)
begin
if (reset)
begin
for(i=0; i<64; i=i+1)
begin
foo <= `SD 64'hdeadbeefbaadbeef; //Initialize to bogus
value
bar <= `SD 0; //Initialize to zero
end
end
end
/code
So when I look at the waveform in make int, bar would be initialized
to all 0's, however, foo gets "NA". I think I'm not doing the array
indexing right. I want each of the 64 foo's to get the bogus value.
Any help would be awesome.
=======================================

we are using fairly new versions/updates of vcs and design compiler.
He's having problems even outside of synthesis, which seems odd. Any
thoughts/ideas? What are we missing here?

We've got it working _other_ than reset fairly well. Just this reset
thing is causing problems.

Thanks very much,
Mark

 

[Homuncilus]

On 2ÔÂ23ČŐ, ÉĎÎç11Ęą36ˇÖ, "Mark Brehob" <bre...@gmail.com> wrote:

Thanks John,

On Feb 22, 3:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

Usually resets get coded as asynchronous resets: always @(posedge clock or
posedge reset) but synchronous can work as well.

Yeah, we avoid async resets mainly because someone always ends up
driving them with
combinational logic and gets killed by glitches.

The initializations are shown but it's not obvious if foo is in the else
side of the if(reset) block.

It is (conditionally) the actual code is:
('SD is just #1, it stands for "Standard Delay")
==========================> // synopsys sync_set_reset "reset"
always @(posedge clock)
begin
if (reset)
begin
for (i=0; i<64; i=i+1)
begin
registers <= `SD 64'hdeadbeefbaadbeef;
free_list <= `SD `NOT_FREE;
valid_list <= `SD `NOT_VALID;
end
end
else
begin
if(wr_en )
begin
registers[wr_prn] <= `SD value_in;
if (valid_in)
valid_list[wr_prn] <= `SD `VALID;
end
end
end
==========================
If the foo assignment is in a different always block, there's a conflict:
apply the reset or the other assignment at the posedge clock?

Nope, this is the only block it is assigned in.
It also isn't an input or output from the module.

If the foo assignment is in the else half of the if(reset) and there is a
clock edge during the reset, the initialization should be golden.

Yeah, I thought so too. I'll try messing around with it some more.

Anyone else have any ideas?

Thanks!

Mark





"Mark Brehob" <bre...@gmail.com> wrote in message

news:1172166364.855274.281220@q2g2000cwa.googlegroups.com...

Hello,
I have a student who is trying to use arrays of buses, something we
normally recommend against.

He asks:
===================================================> > > We want to initialize an array of registers to some value during
reset. However, it's not working out. Here is what I have:
code
reg [6:0] i;
reg [63:0] foo[63:0];
reg [63:0] bar;
always @(posedge clock)
begin
if (reset)
begin
for(i=0; i<64; i=i+1)
begin
foo <= `SD 64'hdeadbeefbaadbeef; //Initialize to bogus
value
bar <= `SD 0; //Initialize to zero
end
end
end
/code
So when I look at the waveform in make int, bar would be initialized
to all 0's, however, foo gets "NA". I think I'm not doing the array
indexing right. I want each of the 64 foo's to get the bogus value.
Any help would be awesome.
======================================
we are using fairly new versions/updates of vcs and design compiler.
He's having problems even outside of synthesis, which seems odd. Any
thoughts/ideas? What are we missing here?

We've got it working _other_ than reset fairly well. Just this reset
thing is causing problems.

Thanks very much,
Mark- Ňţ˛ŘąťŇýÓĂÎÄ×Ö -

- ĎÔĘžŇýÓĂľÄÎÄ×Ö -

I think you can try it after deleting the "`SD".
And you'd best to define the i to integrated type.

 

[John_H]

Mark Brehob wrote:

Thanks John,

On Feb 22, 3:19 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
Usually resets get coded as asynchronous resets: always @(posedge clock or
posedge reset) but synchronous can work as well.

Yeah, we avoid async resets mainly because someone always ends up
driving them with
combinational logic and gets killed by glitches.

The initializations are shown but it's not obvious if foo is in the else
side of the if(reset) block.
It is (conditionally) the actual code is:
('SD is just #1, it stands for "Standard Delay")
===========================
// synopsys sync_set_reset "reset"
always @(posedge clock)
begin
if (reset)
begin
for (i=0; i<64; i=i+1)
begin
registers <= `SD 64'hdeadbeefbaadbeef;
free_list <= `SD `NOT_FREE;
valid_list <= `SD `NOT_VALID;
end
end
else
begin
if(wr_en )
begin
registers[wr_prn] <= `SD value_in;
if (valid_in)
valid_list[wr_prn] <= `SD `VALID;
end
end
end
===========================


If the foo assignment is in a different always block, there's a conflict:
apply the reset or the other assignment at the posedge clock?
Nope, this is the only block it is assigned in.
It also isn't an input or output from the module.

If the foo assignment is in the else half of the if(reset) and there is a
clock edge during the reset, the initialization should be golden.
Yeah, I thought so too. I'll try messing around with it some more.

Anyone else have any ideas?

Thanks!

Mark

If you're having problems simulating the raw RTL, it's bizarre. If the
problem is in synthesis and post-synthesis simulation, it's quite
possible the tool is implementing a RAM construct even though the reset
is included which screams "use registers." If the synthesis tool
implements RAM, you should be able to override the structure with a
synthesis directive.

You have a very bizarre issue here.

Please verify the reset is applied with a clock edge that *should* make
it work. For simulation debug, consider using a $display for at least
one of the "registers" elements. Just to see if the behavior changes
(and isolate a for-statement bug) perhaps change your non-blocking
assignments to blocking assignments in the always block for one
simulation run to see if the behavior changes.

A couple general comments: I see no reason generally to discourage the
use of arrays (and this isn't an array of buses but a simple register
array). I use arrays quite often, mostly for non-resettable memories
but sometimes as registers as well.

Asynchronous resets shouldn't be negatively affected by combinatorial
glitches; if it resets, it resets. There are advantages to using
synchronous resets in logic utilization but simulations are still "not
worthy" in my opinion when it comes to simulating FPGAs that have
default power-up values that the simulation doesn't seen to care about.
To get simulation and synthesis to match, I've resorted to using
"unnecessary" async resets that I feel hinder my logic utilization. If
I could get initial assignments (reg [3:0] foobar = 4'he to work in
simulation and synthesis, perhaps life would be better for me.